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Improved .latch support in BLIF front-end

This commit is contained in:
Clifford Wolf 2015-05-17 18:58:24 +02:00
parent 2cc4e75914
commit 3ecb2bf067
1 changed files with 30 additions and 3 deletions
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33
frontends/blif/blifparse.cc
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@ -120,6 +120,9 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name)
{ {
char *d = strtok(NULL, " \t\r\n"); char *d = strtok(NULL, " \t\r\n");
char *q = strtok(NULL, " \t\r\n"); char *q = strtok(NULL, " \t\r\n");
char *edge = strtok(NULL, " \t\r\n");
char *clock = strtok(NULL, " \t\r\n");
char *init = strtok(NULL, " \t\r\n");
if (module->wires_.count(RTLIL::escape_id(d)) == 0) if (module->wires_.count(RTLIL::escape_id(d)) == 0)
module->addWire(RTLIL::escape_id(d)); module->addWire(RTLIL::escape_id(d));
@ -127,9 +130,33 @@ void parse_blif(RTLIL::Design *design, std::istream &f, std::string dff_name)
if (module->wires_.count(RTLIL::escape_id(q)) == 0) if (module->wires_.count(RTLIL::escape_id(q)) == 0)
module->addWire(RTLIL::escape_id(q)); module->addWire(RTLIL::escape_id(q));
RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name); if (clock == nullptr && edge != nullptr) {
cell->setPort("\\D", module->wires_.at(RTLIL::escape_id(d))); init = edge;
cell->setPort("\\Q", module->wires_.at(RTLIL::escape_id(q))); edge = nullptr;
}
if (init != nullptr && (init[0] == '0' || init[0] == '1'))
module->wire(RTLIL::escape_id(d))->attributes["\\init"] = Const(init[0] == '1' ? 1 : 0, 1);
if (clock == nullptr)
goto no_latch_clock;
if (module->wires_.count(RTLIL::escape_id(clock)) == 0)
module->addWire(RTLIL::escape_id(clock));
if (!strcmp(edge, "re"))
module->addDff(NEW_ID, module->wire(RTLIL::escape_id(clock)),
module->wire(RTLIL::escape_id(d)), module->wire(RTLIL::escape_id(q)));
else if (!strcmp(edge, "fe"))
module->addDff(NEW_ID, module->wire(RTLIL::escape_id(clock)),
module->wire(RTLIL::escape_id(d)), module->wire(RTLIL::escape_id(q)), false);
else {
no_latch_clock:
RTLIL::Cell *cell = module->addCell(NEW_ID, dff_name);
cell->setPort("\\D", module->wires_.at(RTLIL::escape_id(d)));
cell->setPort("\\Q", module->wires_.at(RTLIL::escape_id(q)));
}
continue; continue;
} }