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Merge pull request #1835 from boqwxp/cleanup_sat_expose 

Clean up pseudo-private member usage in `passes/sat/expose.cc`.
This commit is contained in:
Eddie Hung 2020-03-30 13:05:12 -07:00 committed by GitHub
parent 0d878ca256 00544cffab
commit 3e88ede061
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 66 additions and 85 deletions
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151
passes/sat/expose.cc
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@ -53,7 +53,7 @@ bool consider_cell(RTLIL::Design *design, std::set<RTLIL::IdString> &dff_cells,
{ {
if (cell->name[0] == '$' || dff_cells.count(cell->name)) if (cell->name[0] == '$' || dff_cells.count(cell->name))
return false; return false;
if (cell->type[0] == '\\' && !design->modules_.count(cell->type)) if (cell->type[0] == '\\' && (design->module(cell->type) == nullptr))
return false; return false;
return true; return true;
} }
@ -85,27 +85,24 @@ void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module)
SigMap sigmap(module); SigMap sigmap(module);
SigPool dffsignals; SigPool dffsignals;
for (auto &it : module->cells_) { for (auto cell : module->cells()) {
if (ct.cell_known(it.second->type) && it.second->hasPort("\\Q")) if (ct.cell_known(cell->type) && cell->hasPort("\\Q"))
dffsignals.add(sigmap(it.second->getPort("\\Q"))); dffsignals.add(sigmap(cell->getPort("\\Q")));
} }
for (auto &it : module->wires_) { for (auto w : module->wires()) {
if (dffsignals.check_any(it.second)) if (dffsignals.check_any(w))
dff_wires.insert(it.first); dff_wires.insert(w->name);
} }
} }
void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Design *design, RTLIL::Module *module) void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Module *module)
{ {
std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info; std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info;
SigMap sigmap(module); SigMap sigmap(module);
for (auto &it : module->cells_) for (auto cell : module->selected_cells())
{ {
if (!design->selected(module, it.second))
continue;
dff_map_bit_info_t info; dff_map_bit_info_t info;
info.bit_d = RTLIL::State::Sm; info.bit_d = RTLIL::State::Sm;
info.bit_clk = RTLIL::State::Sm; info.bit_clk = RTLIL::State::Sm;
@ -113,7 +110,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
info.clk_polarity = false; info.clk_polarity = false;
info.arst_polarity = false; info.arst_polarity = false;
info.arst_value = RTLIL::State::Sm; info.arst_value = RTLIL::State::Sm;
info.cell = it.second; info.cell = cell;
if (info.cell->type == "$dff") { if (info.cell->type == "$dff") {
info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit(); info.bit_clk = sigmap(info.cell->getPort("\\CLK")).as_bit();
@ -164,12 +161,12 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
} }
std::map<RTLIL::IdString, dff_map_info_t> empty_dq_map; std::map<RTLIL::IdString, dff_map_info_t> empty_dq_map;
for (auto &it : module->wires_) for (auto w : module->wires())
{ {
if (!consider_wire(it.second, empty_dq_map)) if (!consider_wire(w, empty_dq_map))
continue; continue;
std::vector<RTLIL::SigBit> bits_q = sigmap(it.second).to_sigbit_vector(); std::vector<RTLIL::SigBit> bits_q = sigmap(w).to_sigbit_vector();
std::vector<RTLIL::SigBit> bits_d; std::vector<RTLIL::SigBit> bits_d;
std::vector<RTLIL::State> arst_value; std::vector<RTLIL::State> arst_value;
std::set<RTLIL::Cell*> cells; std::set<RTLIL::Cell*> cells;
@ -207,7 +204,7 @@ void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::De
info.arst_value = arst_value; info.arst_value = arst_value;
for (auto it : cells) for (auto it : cells)
info.cells.push_back(it->name); info.cells.push_back(it->name);
map[it.first] = info; map[w->name] = info;
} }
} }
@ -314,26 +311,23 @@ struct ExposePass : public Pass {
RTLIL::Module *first_module = NULL; RTLIL::Module *first_module = NULL;
std::set<RTLIL::IdString> shared_dff_wires; std::set<RTLIL::IdString> shared_dff_wires;
for (auto &mod_it : design->modules_) for (auto mod : design->selected_modules())
{ {
if (!design->selected(mod_it.second)) create_dff_dq_map(dff_dq_maps[mod], mod);
continue;
create_dff_dq_map(dff_dq_maps[mod_it.second], design, mod_it.second);
if (!flag_shared) if (!flag_shared)
continue; continue;
if (first_module == NULL) { if (first_module == NULL) {
for (auto &it : dff_dq_maps[mod_it.second]) for (auto &it : dff_dq_maps[mod])
shared_dff_wires.insert(it.first); shared_dff_wires.insert(it.first);
first_module = mod_it.second; first_module = mod;
} else { } else {
std::set<RTLIL::IdString> new_shared_dff_wires; std::set<RTLIL::IdString> new_shared_dff_wires;
for (auto &it : shared_dff_wires) { for (auto &it : shared_dff_wires) {
if (!dff_dq_maps[mod_it.second].count(it)) if (!dff_dq_maps[mod].count(it))
continue; continue;
if (!compare_wires(first_module->wires_.at(it), mod_it.second->wires_.at(it))) if (!compare_wires(first_module->wire(it), mod->wire(it)))
continue; continue;
new_shared_dff_wires.insert(it); new_shared_dff_wires.insert(it);
} }
@ -364,28 +358,23 @@ struct ExposePass : public Pass {
{ {
RTLIL::Module *first_module = NULL; RTLIL::Module *first_module = NULL;
for (auto &mod_it : design->modules_) for (auto module : design->selected_modules())
{ {
RTLIL::Module *module = mod_it.second;
if (!design->selected(module))
continue;
std::set<RTLIL::IdString> dff_wires; std::set<RTLIL::IdString> dff_wires;
if (flag_dff) if (flag_dff)
find_dff_wires(dff_wires, module); find_dff_wires(dff_wires, module);
if (first_module == NULL) if (first_module == NULL)
{ {
for (auto &it : module->wires_) for (auto w : module->wires())
if (design->selected(module, it.second) && consider_wire(it.second, dff_dq_maps[module])) if (design->selected(module, w) && consider_wire(w, dff_dq_maps[module]))
if (!flag_dff || dff_wires.count(it.first)) if (!flag_dff || dff_wires.count(w->name))
shared_wires.insert(it.first); shared_wires.insert(w->name);
if (flag_evert) if (flag_evert)
for (auto &it : module->cells_) for (auto cell : module->cells())
if (design->selected(module, it.second) && consider_cell(design, dff_cells[module], it.second)) if (design->selected(module, cell) && consider_cell(design, dff_cells[module], cell))
shared_cells.insert(it.first); shared_cells.insert(cell->name);
first_module = module; first_module = module;
} }
@ -397,16 +386,16 @@ struct ExposePass : public Pass {
{ {
RTLIL::Wire *wire; RTLIL::Wire *wire;
if (module->wires_.count(it) == 0) if (module->wire(it) == nullptr)
goto delete_shared_wire; goto delete_shared_wire;
wire = module->wires_.at(it); wire = module->wire(it);
if (!design->selected(module, wire)) if (!design->selected(module, wire))
goto delete_shared_wire; goto delete_shared_wire;
if (!consider_wire(wire, dff_dq_maps[module])) if (!consider_wire(wire, dff_dq_maps[module]))
goto delete_shared_wire; goto delete_shared_wire;
if (!compare_wires(first_module->wires_.at(it), wire)) if (!compare_wires(first_module->wire(it), wire))
goto delete_shared_wire; goto delete_shared_wire;
if (flag_dff && !dff_wires.count(it)) if (flag_dff && !dff_wires.count(it))
goto delete_shared_wire; goto delete_shared_wire;
@ -421,16 +410,16 @@ struct ExposePass : public Pass {
{ {
RTLIL::Cell *cell; RTLIL::Cell *cell;
if (module->cells_.count(it) == 0) if (module->cell(it) == nullptr)
goto delete_shared_cell; goto delete_shared_cell;
cell = module->cells_.at(it); cell = module->cell(it);
if (!design->selected(module, cell)) if (!design->selected(module, cell))
goto delete_shared_cell; goto delete_shared_cell;
if (!consider_cell(design, dff_cells[module], cell)) if (!consider_cell(design, dff_cells[module], cell))
goto delete_shared_cell; goto delete_shared_cell;
if (!compare_cells(first_module->cells_.at(it), cell)) if (!compare_cells(first_module->cell(it), cell))
goto delete_shared_cell; goto delete_shared_cell;
if (0) if (0)
@ -446,13 +435,8 @@ struct ExposePass : public Pass {
} }
} }
for (auto &mod_it : design->modules_) for (auto module : design->selected_modules())
{ {
RTLIL::Module *module = mod_it.second;
if (!design->selected(module))
continue;
std::set<RTLIL::IdString> dff_wires; std::set<RTLIL::IdString> dff_wires;
if (flag_dff && !flag_shared) if (flag_dff && !flag_shared)
find_dff_wires(dff_wires, module); find_dff_wires(dff_wires, module);
@ -461,49 +445,49 @@ struct ExposePass : public Pass {
SigMap out_to_in_map; SigMap out_to_in_map;
for (auto &it : module->wires_) for (auto w : module->wires())
{ {
if (flag_shared) { if (flag_shared) {
if (shared_wires.count(it.first) == 0) if (shared_wires.count(w->name) == 0)
continue; continue;
} else { } else {
if (!design->selected(module, it.second) || !consider_wire(it.second, dff_dq_maps[module])) if (!design->selected(module, w) || !consider_wire(w, dff_dq_maps[module]))
continue; continue;
if (flag_dff && !dff_wires.count(it.first)) if (flag_dff && !dff_wires.count(w->name))
continue; continue;
} }
if (flag_input) if (flag_input)
{ {
if (!it.second->port_input) { if (!w->port_input) {
it.second->port_input = true; w->port_input = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name)); log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
RTLIL::Wire *w = module->addWire(NEW_ID, GetSize(it.second)); RTLIL::Wire *in_wire = module->addWire(NEW_ID, GetSize(w));
out_to_in_map.add(it.second, w); out_to_in_map.add(w, in_wire);
} }
} }
else else
{ {
if (!it.second->port_output) { if (!w->port_output) {
it.second->port_output = true; w->port_output = true;
log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it.second->name)); log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
} }
if (flag_cut) { if (flag_cut) {
RTLIL::Wire *in_wire = add_new_wire(module, it.second->name.str() + sep + "i", it.second->width); RTLIL::Wire *in_wire = add_new_wire(module, w->name.str() + sep + "i", w->width);
in_wire->port_input = true; in_wire->port_input = true;
out_to_in_map.add(sigmap(it.second), in_wire); out_to_in_map.add(sigmap(w), in_wire);
} }
} }
} }
if (flag_input) if (flag_input)
{ {
for (auto &it : module->cells_) { for (auto cell : module->cells()) {
if (!ct.cell_known(it.second->type)) if (!ct.cell_known(cell->type))
continue; continue;
for (auto &conn : it.second->connections_) for (auto &conn : cell->connections_)
if (ct.cell_output(it.second->type, conn.first)) if (ct.cell_output(cell->type, conn.first))
conn.second = out_to_in_map(sigmap(conn.second)); conn.second = out_to_in_map(sigmap(conn.second));
} }
@ -513,11 +497,11 @@ struct ExposePass : public Pass {
if (flag_cut) if (flag_cut)
{ {
for (auto &it : module->cells_) { for (auto cell : module->cells()) {
if (!ct.cell_known(it.second->type)) if (!ct.cell_known(cell->type))
continue; continue;
for (auto &conn : it.second->connections_) for (auto &conn : cell->connections_)
if (ct.cell_input(it.second->type, conn.first)) if (ct.cell_input(cell->type, conn.first))
conn.second = out_to_in_map(sigmap(conn.second)); conn.second = out_to_in_map(sigmap(conn.second));
} }
@ -529,10 +513,10 @@ struct ExposePass : public Pass {
for (auto &dq : dff_dq_maps[module]) for (auto &dq : dff_dq_maps[module])
{ {
if (!module->wires_.count(dq.first)) if (module->wire(dq.first) == nullptr)
continue; continue;
RTLIL::Wire *wire = module->wires_.at(dq.first); RTLIL::Wire *wire = module->wire(dq.first);
std::set<RTLIL::SigBit> wire_bits_set = sigmap(wire).to_sigbit_set(); std::set<RTLIL::SigBit> wire_bits_set = sigmap(wire).to_sigbit_set();
std::vector<RTLIL::SigBit> wire_bits_vec = sigmap(wire).to_sigbit_vector(); std::vector<RTLIL::SigBit> wire_bits_vec = sigmap(wire).to_sigbit_vector();
@ -541,7 +525,7 @@ struct ExposePass : public Pass {
RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0); RTLIL::Wire *wire_dummy_q = add_new_wire(module, NEW_ID, 0);
for (auto &cell_name : info.cells) { for (auto &cell_name : info.cells) {
RTLIL::Cell *cell = module->cells_.at(cell_name); RTLIL::Cell *cell = module->cell(cell_name);
std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort("\\Q")).to_sigbit_vector(); std::vector<RTLIL::SigBit> cell_q_bits = sigmap(cell->getPort("\\Q")).to_sigbit_vector();
for (auto &bit : cell_q_bits) for (auto &bit : cell_q_bits)
if (wire_bits_set.count(bit)) if (wire_bits_set.count(bit))
@ -609,25 +593,22 @@ struct ExposePass : public Pass {
{ {
std::vector<RTLIL::Cell*> delete_cells; std::vector<RTLIL::Cell*> delete_cells;
for (auto &it : module->cells_) for (auto cell : module->cells())
{ {
if (flag_shared) { if (flag_shared) {
if (shared_cells.count(it.first) == 0) if (shared_cells.count(cell->name) == 0)
continue; continue;
} else { } else {
if (!design->selected(module, it.second) || !consider_cell(design, dff_cells[module], it.second)) if (!design->selected(module, cell) || !consider_cell(design, dff_cells[module], cell))
continue; continue;
} }
RTLIL::Cell *cell = it.second; if (design->module(cell->type) != nullptr)
if (design->modules_.count(cell->type))
{ {
RTLIL::Module *mod = design->modules_.at(cell->type); RTLIL::Module *mod = design->module(cell->type);
for (auto &it : mod->wires_) for (auto p : mod->wires())
{ {
RTLIL::Wire *p = it.second;
if (!p->port_input && !p->port_output) if (!p->port_input && !p->port_output)
continue; continue;