inline all tests. Add switch to remove init values as PolarFire DFFs do not support init

techlibs/microchip/synth_microchip.cc

@@ -90,6 +90,9 @@ struct SynthMicrochipPass : public ScriptPass {
 		log("    -noabc9\n");
 		log("        Use classic ABC flow instead of ABC9\n");
 		log("\n");
+		log("    -discard-ffinit\n");
+		log("        discard FF init value instead of emitting an error\n");
+		log("\n");
 		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
@@ -99,6 +102,7 @@ struct SynthMicrochipPass : public ScriptPass {
 	std::string top_opt, edif_file, blif_file, vlog_file, family;
 	bool flatten, retime, noiopad, noclkbuf, nobram, nocarry, nowidelut, nodsp;
 	bool abc9, dff;
+	bool discard_ffinit;
 	int lut_size;
 
 	// debug dump switches
@@ -122,6 +126,7 @@ struct SynthMicrochipPass : public ScriptPass {
 		abc9 = true;
 		dff = false;
 		lut_size = 4;
+		discard_ffinit = false;
 
 		debug_memory = false;
 		debug_carry = false;
@@ -218,6 +223,10 @@ struct SynthMicrochipPass : public ScriptPass {
 				debug_carry = true;
 				continue;
 			}
+			if (args[argidx] == "-discard-ffinit") {
+				discard_ffinit = true;
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -314,6 +323,8 @@ struct SynthMicrochipPass : public ScriptPass {
 			run("opt");
 			run("memory -nomap");
 			run("opt_clean");
+			if (discard_ffinit || help_mode)
+				run("attrmap -remove init", "(only if -discard-ffinit)");
 		}
 
 		if (check_label("map_memory")) {
@@ -454,15 +465,15 @@ struct SynthMicrochipPass : public ScriptPass {
 
 				// D-flop with async reset and enable
 				// posedge CLK, active low reset to 1 or 0, active high EN
-				params += " -cell $_DFFE_PN?P_ 01";
+				params += " -cell $_DFFE_PN?P_ x";
 
 				// D-flop with sync reset and enable, enable takes priority over reset
 				// posedge CLK, active low reset to 1 or 0, active high EN
-				params += " -cell $_SDFFCE_PN?P_ 01";
+				params += " -cell $_SDFFCE_PN?P_ x";
 
 				// D-latch + reset to 0/1
 				// posedge CLK, active low reset to 1 or 0
-				params += " -cell $_DLATCH_PN?_ 01";
+				params += " -cell $_DLATCH_PN?_ x";
 
 				run("dfflegalize" + params, "(Converts FFs to supported types)");
 			}

tests/arch/microchip/dff_opt.v

@@ -1,42 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module dff_opt(
-	input clk,
-	input [1:0] D_comb,
-	input [1:0] EN_comb,
-	input [1:0] RST_comb,
-	output bar
-);
-
-// DFF with enable that can be merged into D
-
-reg foo;
-
-assign bar = foo;
-
-// sync reset
-always@(posedge clk) begin
-	if (&RST_comb) begin
-		foo <= 0;
-	end else begin
-		foo <= &D_comb;
-	end
-end
-
-endmodule

tests/arch/microchip/dff_opt.ys

@@ -14,10 +14,28 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-read_verilog dff_opt.v 
 
+# reset can be merged into D LUT
+read_verilog <<EOT
+module dff_opt(
+	input clk,
+	input [1:0] D_comb,
+	input [1:0] EN_comb,
+	input [1:0] RST_comb,
+	output bar
+);
+reg foo;
+assign bar = foo;
+always@(posedge clk) begin
+	if (&RST_comb) begin
+		foo <= 0;
+	end else begin
+		foo <= &D_comb;
+	end
+end
+endmodule
+EOT
 synth_microchip -top dff_opt -family polarfire -noiopad
-
 select -assert-count 1 t:SLE
 select -assert-count 1 t:CFG4
 select -assert-count 1 t:CLKBUF

tests/arch/microchip/ram_SDP.v

@@ -1,39 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module ram_SDP(data,waddr,we,clk,q);
-parameter d_width = 32;
-parameter addr_width = 8;
-parameter mem_depth = 256;
-input [d_width-1:0] data;
-input [addr_width-1:0] waddr;
-input we, clk;
-output reg [d_width-1:0] q;
-
-reg [d_width-1:0] mem [mem_depth-1:0];
-
-always @(posedge clk) begin
-	if (we) begin 
-		mem[waddr] <= data;
-	end else begin
-		q <= mem[waddr];
-	end
-end
-
-endmodule
-

tests/arch/microchip/ram_SDP.ys

@@ -14,7 +14,27 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-read_verilog ram_SDP.v
+read_verilog <<EOT
+module ram_SDP(data,waddr,we,clk,q);
+parameter d_width = 32;
+parameter addr_width = 8;
+parameter mem_depth = 256;
+input [d_width-1:0] data;
+input [addr_width-1:0] waddr;
+input we, clk;
+output reg [d_width-1:0] q;
+
+reg [d_width-1:0] mem [mem_depth-1:0];
+
+always @(posedge clk) begin
+	if (we) begin 
+		mem[waddr] <= data;
+	end else begin
+		q <= mem[waddr];
+	end
+end
+endmodule
+EOT
 synth_microchip -top ram_SDP -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
 select -assert-count 1 t:CFG1

tests/arch/microchip/ram_TDP.v

@@ -1,52 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module ram_TDP (clka,clkb,wea,addra,dataina,qa,web,addrb,datainb,qb);
-parameter addr_width = 10;
-parameter data_width = 2;
-input clka,clkb,wea,web;
-input [data_width - 1 : 0] dataina,datainb;
-input [addr_width - 1 : 0] addra,addrb;
-output reg [data_width - 1 : 0] qa,qb;
-reg [addr_width - 1 : 0] addra_reg, addrb_reg;
-reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
-
-always @ (posedge clka)
-begin
-	addra_reg <= addra;
-			
-	if(wea) begin
-		mem[addra] <= dataina;
-		qa <= dataina;
-	end else begin
-		qa <= mem[addra];
-	end
-end
-
-always @ (posedge clkb)
-begin
-	addrb_reg <= addrb;
-	if(web) begin
-		mem[addrb] <= datainb;
-		qb <= datainb;
-	end else begin
-		qb <= mem[addrb];
-	end
-end
-
-endmodule

tests/arch/microchip/ram_TDP.ys

@@ -14,7 +14,41 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-read_verilog ram_TDP.v
+read_verilog <<EOT
+module ram_TDP (clka,clkb,wea,addra,dataina,qa,web,addrb,datainb,qb);
+parameter addr_width = 10;
+parameter data_width = 2;
+input clka,clkb,wea,web;
+input [data_width - 1 : 0] dataina,datainb;
+input [addr_width - 1 : 0] addra,addrb;
+output reg [data_width - 1 : 0] qa,qb;
+reg [addr_width - 1 : 0] addra_reg, addrb_reg;
+reg [data_width - 1 : 0] mem [(2**addr_width) - 1 : 0];
+
+always @ (posedge clka)
+begin
+	addra_reg <= addra;
+			
+	if(wea) begin
+		mem[addra] <= dataina;
+		qa <= dataina;
+	end else begin
+		qa <= mem[addra];
+	end
+end
+
+always @ (posedge clkb)
+begin
+	addrb_reg <= addrb;
+	if(web) begin
+		mem[addrb] <= datainb;
+		qb <= datainb;
+	end else begin
+		qb <= mem[addrb];
+	end
+end
+endmodule
+EOT
 synth_microchip -top ram_TDP -family polarfire -noiopad
 select -assert-count 1 t:RAM1K20
 select -assert-none t:RAM1K20 %% t:* %D

tests/arch/microchip/reduce.v

@@ -1,29 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module reduce(
-	input [7:0] data,
-	output Y
-
-);
-
-
-assign Y = ^data;
-
-endmodule
-

tests/arch/microchip/reduce.ys

@@ -14,10 +14,15 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-read_verilog reduce.v
+read_verilog <<EOT
-
+module reduce(
+	input [7:0] data,
+	output Y
+);
+	assign Y = ^data;
+endmodule
+EOT
 synth_microchip -top reduce -family polarfire -noiopad
-
 select -assert-count 1 t:XOR8
 select -assert-none t:XOR8 %% t:* %D
 

tests/arch/microchip/uram_ar.v

@@ -1,38 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module uram_ar(data,waddr,we,clk,q);
-parameter d_width = 12;
-parameter addr_width = 2;
-parameter mem_depth = 12;
-input [d_width-1:0] data;
-input [addr_width-1:0] waddr;
-input we, clk;
-output [d_width-1:0] q;
-
-reg [d_width-1:0] mem [mem_depth-1:0];
-
-assign q = mem[waddr];
-
-always @(posedge clk) begin
-	if (we) 
-		mem[waddr] <= data;
-
-end
-
-endmodule

tests/arch/microchip/uram_ar.ys

@@ -14,9 +14,27 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-read_verilog uram_ar.v
+read_verilog <<EOT
+module uram_ar(data,waddr,we,clk,q);
+parameter d_width = 12;
+parameter addr_width = 2;
+parameter mem_depth = 12;
+input [d_width-1:0] data;
+input [addr_width-1:0] waddr;
+input we, clk;
+output [d_width-1:0] q;
+
+reg [d_width-1:0] mem [mem_depth-1:0];
+assign q = mem[waddr];
+
+always @(posedge clk) begin
+	if (we) 
+		mem[waddr] <= data;
+
+end
+endmodule
+EOT
 
 synth_microchip -top uram_ar -family polarfire -noiopad
-
 select -assert-count 1 t:RAM64x12
 select -assert-none t:RAM64x12 %% t:* %D

tests/arch/microchip/uram_sr.v

@@ -1,40 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module uram_sr(clk, wr, raddr, din, waddr, dout);
-	input clk;
-	input [11:0] din;
-	input wr;
-	input [5:0] waddr, raddr;
-	output [11:0] dout;
-	reg [5:0] raddr_reg;
-	reg [11:0] mem [0:63];
-	assign dout = mem[raddr_reg];
-
-	integer i;
-	initial begin
-		for (i = 0; i < 64; i = i + 1) begin
-			mem[i] = 12'hfff;
-		end
-	end
-
-	always@(posedge clk) begin
-		raddr_reg <= raddr; if(wr)
-		mem[waddr]<= din;
-	end
-endmodule

tests/arch/microchip/uram_sr.ys

@@ -14,7 +14,30 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-read_verilog uram_sr.v
+read_verilog <<EOT
+module uram_sr(clk, wr, raddr, din, waddr, dout);
+	input clk;
+	input [11:0] din;
+	input wr;
+	input [5:0] waddr, raddr;
+	output [11:0] dout;
+	reg [5:0] raddr_reg;
+	reg [11:0] mem [0:63];
+	assign dout = mem[raddr_reg];
+	integer i;
+	initial begin
+		for (i = 0; i < 64; i = i + 1) begin
+			mem[i] = 12'hfff;
+		end
+	end
+
+	always@(posedge clk) begin
+		raddr_reg <= raddr; 
+		if(wr)
+			mem[waddr]<= din;
+	end
+endmodule
+EOT
 
 synth_microchip -top uram_sr -family polarfire -noiopad
 

tests/arch/microchip/widemux.v

@@ -1,31 +0,0 @@
-/*
-ISC License
-
-Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries
-
-Permission to use, copy, modify, and/or distribute this software for any
-purpose with or without fee is hereby granted, provided that the above
-copyright notice and this permission notice appear in all copies.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-*/
-
-module widemux(
-	input [3:0] data,
-	input S0,
-	input S1,
-	output Y
-
-);
-assign Y = S1 ? (S0 ? data[3] : data[1]) : (S0 ? data[2] : data[0]);
-
-endmodule
-
-
-

tests/arch/microchip/widemux.ys

@@ -14,14 +14,20 @@
 # ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
 # OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 
-read_verilog widemux.v
+read_verilog <<EOT
-
+module widemux(
+	input [3:0] data,
+	input S0,
+	input S1,
+	output Y
+);
+	assign Y = S1 ? (S0 ? data[3] : data[1]) : (S0 ? data[2] : data[0]);
+endmodule
+EOT
 synth_microchip -top widemux -family polarfire -noiopad
-
 select -assert-count 1 t:MX4
 select -assert-none t:MX4 %% t:* %D
 
-
 # RTL style is different here forming a different structure
 read_verilog ../common/mux.v
 design -save read