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intel_alm: add $__ prefix to MISTRAL_FF_SYNCONLY

This commit is contained in:
Eddie Hung 2020-05-25 15:15:20 -07:00 committed by Marcelina Kościelnicka
parent 83cde2d02b
commit 3db3e1e149
4 changed files with 4 additions and 4 deletions
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2
techlibs/intel_alm/common/abc9_map.v
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@ -11,7 +11,7 @@ parameter _TECHMAP_CONSTMSK_ACLR_ = 1'b0;
// If the async-clear is constant, we assume it's disabled. // If the async-clear is constant, we assume it's disabled.
if (_TECHMAP_CONSTMSK_ACLR_ != 1'b0) if (_TECHMAP_CONSTMSK_ACLR_ != 1'b0)
MISTRAL_FF_SYNCONLY _TECHMAP_REPLACE_ (.DATAIN(DATAIN), .CLK(CLK), .ENA(ENA), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q)); $__MISTRAL_FF_SYNCONLY _TECHMAP_REPLACE_ (.DATAIN(DATAIN), .CLK(CLK), .ENA(ENA), .SCLR(SCLR), .SLOAD(SLOAD), .SDATA(SDATA), .Q(Q));
else else
wire _TECHMAP_FAIL_ = 1; wire _TECHMAP_FAIL_ = 1;

2
techlibs/intel_alm/common/abc9_model.v
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@ -18,7 +18,7 @@
// This is a purely-synchronous flop, that ABC9 can use for sequential synthesis. // This is a purely-synchronous flop, that ABC9 can use for sequential synthesis.
(* abc9_flop, lib_whitebox *) (* abc9_flop, lib_whitebox *)
module MISTRAL_FF_SYNCONLY( module $__MISTRAL_FF_SYNCONLY (
input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA, input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA,
output reg Q output reg Q
); );

2
techlibs/intel_alm/common/abc9_unmap.v
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@ -1,7 +1,7 @@
// After performing sequential synthesis, map the synchronous flops back to // After performing sequential synthesis, map the synchronous flops back to
// standard MISTRAL_FF flops. // standard MISTRAL_FF flops.
module MISTRAL_FF_SYNCONLY( module $__MISTRAL_FF_SYNCONLY (
input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA, input DATAIN, CLK, ENA, SCLR, SLOAD, SDATA,
output reg Q output reg Q
); );

2
techlibs/intel_alm/synth_intel_alm.cc
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@ -173,7 +173,7 @@ struct SynthIntelALMPass : public ScriptPass {
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/alm_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/dff_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/mem_sim.v", family_opt.c_str()));
run(stringf("read_verilog -specify -lib -D %s +/intel_alm/common/abc9_model.v", family_opt.c_str())); run(stringf("read_verilog -specify -lib -D %s -icells +/intel_alm/common/abc9_model.v", family_opt.c_str()));
// Misc and common cells // Misc and common cells
run("read_verilog -lib +/intel/common/altpll_bb.v"); run("read_verilog -lib +/intel/common/altpll_bb.v");