From c01ff05fabe948acfbbb259e92b3bd0009bd068e Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Mon, 4 Apr 2016 16:56:43 -0700 Subject: [PATCH 1/5] Added GP_BANDGAP cell --- techlibs/greenpak4/cells_sim.v | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index 4ea576960..d98526215 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -144,3 +144,12 @@ module GP_SYSRESET(input RST); //cannot simulate whole system reset endmodule + +module GP_BANDGAP(output reg OK, output reg VOUT); + parameter AUTO_PWRDN = 1; + parameter CHOPPER_EN = 1; + parameter OUT_DELAY = 100; + + //cannot simulate mixed signal IP + +endmodule From c2b909c051edf189d6e1f807bb367c3c543dc058 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Mon, 4 Apr 2016 21:46:07 -0700 Subject: [PATCH 2/5] Added GP_POR --- techlibs/greenpak4/cells_sim.v | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index d98526215..f013d9b71 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -153,3 +153,25 @@ module GP_BANDGAP(output reg OK, output reg VOUT); //cannot simulate mixed signal IP endmodule + + +module GP_POR(output reg RST_DONE); + parameter POR_TIME = 500; + + initial begin + RST_DONE = 0; + + if(POR_TIME == 4) + #4000; + else if(POR_TIME == 500) + #500000; + else begin + $display("ERROR: bad POR_TIME for GP_POR cell"); + $finish; + end + + RST_DONE = 1; + + end + +endmodule From 1df559c7062b62a8b72b70d40d65da99667a2183 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Wed, 6 Apr 2016 22:40:25 -0700 Subject: [PATCH 3/5] Added GP_RINGOSC primitive --- techlibs/greenpak4/cells_sim.v | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index f013d9b71..d3a176b88 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -75,6 +75,9 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT); initial CLKOUT = 0; + //auto powerdown not implemented for simulation + //output dividers not implemented for simulation + always begin if(PWRDN) clkout = 0; @@ -87,6 +90,29 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT); endmodule +module GP_RINGOSC(input PWRDN, output reg CLKOUT); + + parameter PWRDN_EN = 0; + parameter AUTO_PWRDN = 0; + parameter OUT_DIV = 1; + + initial CLKOUT = 0; + + //output dividers not implemented for simulation + //auto powerdown not implemented for simulation + + always begin + if(PWRDN) + clkout = 0; + else begin + //half period of 27 MHz + #18.518; + clkout = ~clkout; + end + end + +endmodule + module GP_COUNT8(input CLK, input wire RST, output reg OUT); parameter RESET_MODE = "RISING"; From 48c10d90f4b8c813782d4c5a304b2e1e24d140d8 Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Wed, 6 Apr 2016 23:10:34 -0700 Subject: [PATCH 4/5] Added second divider to GP_RINGOSC --- techlibs/greenpak4/cells_sim.v | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/techlibs/greenpak4/cells_sim.v b/techlibs/greenpak4/cells_sim.v index d3a176b88..1234ce1b2 100644 --- a/techlibs/greenpak4/cells_sim.v +++ b/techlibs/greenpak4/cells_sim.v @@ -80,34 +80,39 @@ module GP_LFOSC(input PWRDN, output reg CLKOUT); always begin if(PWRDN) - clkout = 0; + CLKOUT = 0; else begin //half period of 1730 Hz #289017; - clkout = ~clkout; + CLKOUT = ~CLKOUT; end end endmodule -module GP_RINGOSC(input PWRDN, output reg CLKOUT); +module GP_RINGOSC(input PWRDN, output reg CLKOUT_PREDIV, output reg CLKOUT_FABRIC); parameter PWRDN_EN = 0; parameter AUTO_PWRDN = 0; - parameter OUT_DIV = 1; + parameter PRE_DIV = 1; + parameter FABRIC_DIV = 1; - initial CLKOUT = 0; + initial CLKOUT_PREDIV = 0; + initial CLKOUT_FABRIC = 0; //output dividers not implemented for simulation //auto powerdown not implemented for simulation always begin - if(PWRDN) - clkout = 0; + if(PWRDN) begin + CLKOUT_PREDIV = 0; + CLKOUT_FABRIC = 0; + end else begin //half period of 27 MHz #18.518; - clkout = ~clkout; + CLKOUT_PREDIV = ~CLKOUT_PREDIV; + CLKOUT_FABRIC = ~CLKOUT_FABRIC; end end From 01a5f711871658c9997f7352414cd4ac50ed772c Mon Sep 17 00:00:00 2001 From: Andrew Zonenberg Date: Wed, 6 Apr 2016 23:42:22 -0700 Subject: [PATCH 5/5] Fixed assertion failure for non-inferrable counters in some cases --- techlibs/greenpak4/greenpak4_counters.cc | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/techlibs/greenpak4/greenpak4_counters.cc b/techlibs/greenpak4/greenpak4_counters.cc index 394f3dab1..7b5646bf2 100644 --- a/techlibs/greenpak4/greenpak4_counters.cc +++ b/techlibs/greenpak4/greenpak4_counters.cc @@ -248,8 +248,12 @@ void greenpak4_counters_worker( if (cell->type != "$alu") return; - //A input is the count value. Check if it has COUNT_EXTRACT set - RTLIL::Wire* a_wire = sigmap(cell->getPort("\\A")).as_wire(); + //A input is the count value. Check if it has COUNT_EXTRACT set. + //If it's not a wire, don't even try + auto port = sigmap(cell->getPort("\\A")); + if(!port.is_wire()) + return; + RTLIL::Wire* a_wire = port.as_wire(); bool force_extract = false; bool never_extract = false; string count_reg_src = a_wire->attributes["\\src"].decode_string().c_str();