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Progress in presentation

This commit is contained in:
Clifford Wolf 2014-02-18 19:37:39 +01:00
parent a71d09421d
commit 3d9da919d8
6 changed files with 72 additions and 3 deletions
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37
manual/PRESENTATION_ExAdv.tex
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@ -406,7 +406,42 @@ input values to cells.
\subsubsection{Handling shorted inputs}
\begin{frame}{\subsubsecname}
TBD
\begin{itemize}
\item The special parameters {\tt \_TECHMAP\_BITS\_CONNMAP\_} and
{\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} can be used to handle shorted inputs.
\medskip
\item Each bit of the port correlates to an {\tt \_TECHMAP\_BITS\_CONNMAP\_} bits wide
number in {\tt \_TECHMAP\_CONNMAP\_\it <port-name>\tt \_}.
\medskip
\item Each unique signal bit is assigned its own number. Identical fields in the {\tt
\_TECHMAP\_CONNMAP\_\it <port-name>\tt \_} parameters mean shorted signal bits.
\medskip
\item The numbers 0-3 are reserved for {\tt 0}, {\tt 1}, {\tt x}, and {\tt z} respectively.
\medskip
\item Example use-cases:
\begin{itemize}
\item Detecting shared clock or control signals in memory interfaces.
\item In some cases this can be used for for optimization.
\end{itemize}
\end{itemize}
\end{frame}
\begin{frame}[t]{\subsubsecname{} -- Example}
\vbox to 0cm{
\vskip4.5cm
\hskip6.5cm\includegraphics[width=5cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/addshift.pdf}
\vss
}
\vskip-0.6cm
\begin{columns}
\column[t]{6cm}
\vskip-0.4cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{7pt}{8pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/addshift_map.v}
\column[t]{4.2cm}
\vskip-0.6cm
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/addshift_test.v}
\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=5]{PRESENTATION_ExAdv/addshift_test.ys}
\end{columns}
\end{frame}
\subsubsection{Notes on using techmap}

5
manual/PRESENTATION_ExAdv/Makefile
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@ -1,5 +1,5 @@
all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf
all: select_01.pdf red_or3x1.pdf sym_mul.pdf mymul.pdf mulshift.pdf addshift.pdf
select_01.pdf: select_01.v select_01.ys
../../yosys select_01.ys
@ -16,3 +16,6 @@ mymul.pdf: mymul_*
mulshift.pdf: mulshift_*
../../yosys mulshift_test.ys
addshift.pdf: addshift_*
../../yosys addshift_test.ys

20
manual/PRESENTATION_ExAdv/addshift_map.v Normal file
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@ -0,0 +1,20 @@
module \$add (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
parameter _TECHMAP_BITS_CONNMAP_ = 0;
parameter _TECHMAP_CONNMAP_A_ = 0;
parameter _TECHMAP_CONNMAP_B_ = 0;
wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH < Y_WIDTH ||
_TECHMAP_CONNMAP_A_ != _TECHMAP_CONNMAP_B_;
assign Y = A << 1;
endmodule

5
manual/PRESENTATION_ExAdv/addshift_test.v Normal file
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@ -0,0 +1,5 @@
module test (A, B, X, Y);
input [7:0] A, B;
output [7:0] X = A + B;
output [7:0] Y = A + A;
endmodule

6
manual/PRESENTATION_ExAdv/addshift_test.ys Normal file
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@ -0,0 +1,6 @@
read_verilog addshift_test.v
hierarchy -check -top test
techmap -map addshift_map.v;;
show -prefix addshift -format pdf -notitle

2
manual/PRESENTATION_Intro.tex
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@ -359,7 +359,7 @@ as Qflow\footnote[frame]{\url{http://opencircuitdesign.com/qflow/}} for ASIC des
Map registers to available hardware flip-flops.
}%
\only<12>{
Map logix to available hardware gates.
Map logic to available hardware gates.
}%
\only<13>{
Clean up the design (just the last step of {\tt opt}).