mirror of https://github.com/YosysHQ/yosys.git
Use ID() macro
This commit is contained in:
Eddie Hung
parent
a29814ca3f
commit
3d3779b037
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@ -83,52 +83,51 @@ struct ExtSigSpec {
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bool operator==(const ExtSigSpec &other) const { return is_signed == other.is_signed && sign == other.sign && sig == other.sig && semantics == other.semantics; }
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};
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#define BITWISE_OPS "$_AND_", "$_NAND_", "$_OR_", "$_NOR_", "$_XOR_", "$_XNOR_", "$_ANDNOT_", "$_ORNOT_", "$and", "$or", "$xor", "$xnor"
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#define BITWISE_OPS ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_ANDNOT_), ID($_ORNOT_), ID($and), ID($or), ID($xor), ID($xnor)
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#define REDUCTION_OPS "$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool", "$reduce_nand"
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#define REDUCTION_OPS ID($reduce_and), ID($reduce_or), ID($reduce_xor), ID($reduce_xnor), ID($reduce_bool), ID($reduce_nand)
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#define LOGICAL_OPS "$logic_and", "$logic_or"
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#define LOGICAL_OPS ID($logic_and), ID($logic_or)
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#define SHIFT_OPS "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx"
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#define SHIFT_OPS ID($shl), ID($shr), ID($sshl), ID($sshr), ID($shift), ID($shiftx)
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#define RELATIONAL_OPS "$lt", "$le", "$eq", "$ne", "$eqx", "$nex", "$ge", "$gt"
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#define RELATIONAL_OPS ID($lt), ID($le), ID($eq), ID($ne), ID($eqx), ID($nex), ID($ge), ID($gt)
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bool cell_supported(RTLIL::Cell *cell)
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{
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if (cell->type.in("$alu")) {
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RTLIL::SigSpec sig_bi = cell->getPort("\\BI");
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RTLIL::SigSpec sig_ci = cell->getPort("\\CI");
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if (cell->type.in(ID($alu))) {
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RTLIL::SigSpec sig_bi = cell->getPort(ID(BI));
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RTLIL::SigSpec sig_ci = cell->getPort(ID(CI));
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if (sig_bi.is_fully_const() && sig_ci.is_fully_const() && sig_bi == sig_ci)
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return true;
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} else if (cell->type.in(LOGICAL_OPS, SHIFT_OPS, BITWISE_OPS, RELATIONAL_OPS, "$add", "$sub", "$mul", "$div", "$mod", "$concat")) {
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} else if (cell->type.in(LOGICAL_OPS, SHIFT_OPS, BITWISE_OPS, RELATIONAL_OPS, ID($add), ID($sub), ID($mul), ID($div), ID($mod), ID($concat))) {
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return true;
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}
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return false;
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}
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std::map<std::string, std::string> mergeable_type_map{
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{"$sub", "$add"},
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std::map<IdString, IdString> mergeable_type_map{
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{ID($sub), ID($add)},
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};
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bool mergeable(RTLIL::Cell *a, RTLIL::Cell *b)
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{
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auto a_type = a->type;
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if (mergeable_type_map.count(a_type.str()))
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a_type = mergeable_type_map.at(a_type.str());
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if (mergeable_type_map.count(a_type))
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a_type = mergeable_type_map.at(a_type);
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auto b_type = b->type;
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if (mergeable_type_map.count(b_type.str()))
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b_type = mergeable_type_map.at(b_type.str());
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if (mergeable_type_map.count(b_type))
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b_type = mergeable_type_map.at(b_type);
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return a_type == b_type;
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}
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RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_name)
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{
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if (cell->type.in("$lt", "$le", "$ge", "$gt", "$div", "$mod", "$concat", SHIFT_OPS) && port_name == "\\B")
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if (cell->type.in(ID($lt), ID($le), ID($ge), ID($gt), ID($div), ID($mod), ID($concat), SHIFT_OPS) && port_name == ID(B))
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return port_name;
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return "";
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@ -136,9 +135,9 @@ RTLIL::IdString decode_port_semantics(RTLIL::Cell *cell, RTLIL::IdString port_na
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RTLIL::SigSpec decode_port_sign(RTLIL::Cell *cell, RTLIL::IdString port_name) {
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if (cell->type == "$alu" && port_name == "\\B")
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return cell->getPort("\\BI");
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else if (cell->type == "$sub" && port_name == "\\B")
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if (cell->type == ID($alu) && port_name == ID(B))
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return cell->getPort(ID(BI));
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else if (cell->type == ID($sub) && port_name == ID(B))
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return RTLIL::Const(1, 1);
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return RTLIL::Const(0, 1);
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@ -153,7 +152,6 @@ bool decode_port_signed(RTLIL::Cell *cell, RTLIL::IdString port_name)
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return cell->getParam(port_name.str() + "_SIGNED").as_bool();
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return false;
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}
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ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, SigMap *sigmap)
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@ -170,15 +168,14 @@ ExtSigSpec decode_port(RTLIL::Cell *cell, RTLIL::IdString port_name, SigMap *sig
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void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<OpMuxConn> &ports, const ExtSigSpec &operand)
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{
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std::vector<ExtSigSpec> muxed_operands;
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int max_width = 0;
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for (const auto& p : ports) {
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auto op = p.op;
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RTLIL::IdString muxed_port_name = "\\A";
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if (decode_port(op, "\\A", &assign_map) == operand)
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muxed_port_name = "\\B";
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RTLIL::IdString muxed_port_name = ID(A);
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if (decode_port(op, ID(A), &assign_map) == operand)
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muxed_port_name = ID(B);
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auto operand = decode_port(op, muxed_port_name, &assign_map);
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if (operand.sig.size() > max_width)
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@ -190,8 +187,7 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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auto shared_op = ports[0].op;
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if (std::any_of(muxed_operands.begin(), muxed_operands.end(), [&](ExtSigSpec &op) { return op.sign != muxed_operands[0].sign; }))
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if (max_width < shared_op->getParam("\\Y_WIDTH").as_int())
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max_width = shared_op->getParam("\\Y_WIDTH").as_int();
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max_width = std::max(max_width, shared_op->getParam(ID(Y_WIDTH)).as_int());
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for (auto &operand : muxed_operands)
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@ -208,11 +204,10 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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if (muxed_op.sign != muxed_operands[0].sign)
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muxed_op = ExtSigSpec(module->Neg(NEW_ID, muxed_op.sig, muxed_op.is_signed));
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RTLIL::SigSpec mux_y = mux->getPort("\\Y");
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RTLIL::SigSpec mux_a = mux->getPort("\\A");
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RTLIL::SigSpec mux_b = mux->getPort("\\B");
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RTLIL::SigSpec mux_s = mux->getPort("\\S");
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RTLIL::SigSpec mux_y = mux->getPort(ID(Y));
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RTLIL::SigSpec mux_a = mux->getPort(ID(A));
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RTLIL::SigSpec mux_b = mux->getPort(ID(B));
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RTLIL::SigSpec mux_s = mux->getPort(ID(S));
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RTLIL::SigSpec shared_pmux_a = RTLIL::Const(RTLIL::State::Sx, max_width);
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RTLIL::SigSpec shared_pmux_b;
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@ -221,49 +216,48 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
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int conn_width = ports[0].sig.size();
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int conn_offset = ports[0].mux_port_offset;
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shared_op->setPort("\\Y", shared_op->getPort("\\Y").extract(0, conn_width));
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shared_op->setPort(ID(Y), shared_op->getPort(ID(Y)).extract(0, conn_width));
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if (mux->type == "$pmux") {
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if (mux->type == ID($pmux)) {
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shared_pmux_s = RTLIL::SigSpec();
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for (const auto &p : ports) {
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shared_pmux_s.append(mux_s[p.mux_port_id]);
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mux_b.replace(p.mux_port_id * mux_a.size() + conn_offset, shared_op->getPort("\\Y"));
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mux_b.replace(p.mux_port_id * mux_a.size() + conn_offset, shared_op->getPort(ID(Y)));
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}
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} else {
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shared_pmux_s = RTLIL::SigSpec{mux_s, module->Not(NEW_ID, mux_s)};
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mux_a.replace(conn_offset, shared_op->getPort("\\Y"));
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mux_b.replace(conn_offset, shared_op->getPort("\\Y"));
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mux_a.replace(conn_offset, shared_op->getPort(ID(Y)));
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mux_b.replace(conn_offset, shared_op->getPort(ID(Y)));
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}
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mux->setPort("\\A", mux_a);
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mux->setPort("\\B", mux_b);
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mux->setPort("\\Y", mux_y);
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mux->setPort("\\S", mux_s);
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mux->setPort(ID(A), mux_a);
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mux->setPort(ID(B), mux_b);
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mux->setPort(ID(Y), mux_y);
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mux->setPort(ID(S), mux_s);
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for (const auto &op : muxed_operands)
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shared_pmux_b.append(op.sig);
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auto mux_to_oper = module->Pmux(NEW_ID, shared_pmux_a, shared_pmux_b, shared_pmux_s);
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if (shared_op->type.in("$alu")) {
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RTLIL::SigSpec alu_x = shared_op->getPort("\\X");
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RTLIL::SigSpec alu_co = shared_op->getPort("\\CO");
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if (shared_op->type.in(ID($alu))) {
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RTLIL::SigSpec alu_x = shared_op->getPort(ID(X));
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RTLIL::SigSpec alu_co = shared_op->getPort(ID(CO));
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shared_op->setPort("\\X", alu_x.extract(0, conn_width));
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shared_op->setPort("\\CO", alu_co.extract(0, conn_width));
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shared_op->setPort(ID(X), alu_x.extract(0, conn_width));
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shared_op->setPort(ID(CO), alu_co.extract(0, conn_width));
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}
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shared_op->setParam("\\Y_WIDTH", conn_width);
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shared_op->setParam(ID(Y_WIDTH), conn_width);
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if (decode_port(shared_op, "\\A", &assign_map) == operand) {
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shared_op->setPort("\\B", mux_to_oper);
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shared_op->setParam("\\B_WIDTH", max_width);
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if (decode_port(shared_op, ID(A), &assign_map) == operand) {
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shared_op->setPort(ID(B), mux_to_oper);
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shared_op->setParam(ID(B_WIDTH), max_width);
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} else {
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shared_op->setPort("\\A", mux_to_oper);
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shared_op->setParam("\\A_WIDTH", max_width);
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shared_op->setPort(ID(A), mux_to_oper);
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shared_op->setParam(ID(A_WIDTH), max_width);
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}
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}
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typedef struct {
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@ -285,7 +279,6 @@ template <typename T> void remove_val(std::vector<T> &v, const std::vector<T> &v
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void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpec &shared_operand)
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{
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auto it = ports.begin();
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ExtSigSpec seed;
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@ -293,9 +286,9 @@ void check_muxed_operands(std::vector<const OpMuxConn *> &ports, const ExtSigSpe
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auto p = *it;
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auto op = p->op;
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RTLIL::IdString muxed_port_name = "\\A";
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if (decode_port(op, "\\A", &assign_map) == shared_operand) {
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muxed_port_name = "\\B";
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RTLIL::IdString muxed_port_name = ID(A);
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if (decode_port(op, ID(A), &assign_map) == shared_operand) {
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muxed_port_name = ID(B);
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}
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auto operand = decode_port(op, muxed_port_name, &assign_map);
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@ -322,7 +315,7 @@ ExtSigSpec find_shared_operand(const OpMuxConn* seed, std::vector<const OpMuxCon
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auto op_a = seed->op;
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for (RTLIL::IdString port_name : {"\\A", "\\B"}) {
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for (RTLIL::IdString port_name : {ID(A), ID(B)}) {
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oper = decode_port(op_a, port_name, &assign_map);
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auto operand_users = operand_to_users.at(oper);
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@ -362,78 +355,77 @@ dict<RTLIL::SigSpec, OpMuxConn> find_valid_op_mux_conns(RTLIL::Module *module, d
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std::function<void(RTLIL::SigBit)> remove_outsig_from_aux_bit = [&](RTLIL::SigBit auxbit) {
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auto aux_outsig = op_aux_to_outsig.at(auxbit);
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auto op = outsig_to_operator.at(aux_outsig);
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auto op_outsig = assign_map(op->getPort("\\Y"));
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auto op_outsig = assign_map(op->getPort(ID(Y)));
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remove_outsig(op_outsig);
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for (auto aux_outbit : aux_outsig)
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op_aux_to_outsig.erase(aux_outbit);
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};
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std::function<void(RTLIL::Cell *)>
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find_op_mux_conns = [&](RTLIL::Cell *mux) {
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RTLIL::SigSpec sig;
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int mux_port_size;
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std::function<void(RTLIL::Cell *)> find_op_mux_conns = [&](RTLIL::Cell *mux) {
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RTLIL::SigSpec sig;
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int mux_port_size;
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if (mux->type.in("$mux", "$_MUX_")) {
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mux_port_size = mux->getPort("\\A").size();
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sig = RTLIL::SigSpec{mux->getPort("\\B"), mux->getPort("\\A")};
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} else {
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mux_port_size = mux->getPort("\\A").size();
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sig = mux->getPort("\\B");
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}
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if (mux->type.in(ID($mux), ID($_MUX_))) {
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mux_port_size = mux->getPort(ID(A)).size();
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sig = RTLIL::SigSpec{mux->getPort(ID(B)), mux->getPort(ID(A))};
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} else {
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mux_port_size = mux->getPort(ID(A)).size();
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sig = mux->getPort(ID(B));
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}
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auto mux_insig = assign_map(sig);
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auto mux_insig = assign_map(sig);
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for (int i = 0; i < mux_insig.size(); ++i) {
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if (op_aux_to_outsig.count(mux_insig[i])) {
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remove_outsig_from_aux_bit(mux_insig[i]);
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continue;
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}
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for (int i = 0; i < mux_insig.size(); ++i) {
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if (op_aux_to_outsig.count(mux_insig[i])) {
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remove_outsig_from_aux_bit(mux_insig[i]);
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continue;
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}
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if (!op_outbit_to_outsig.count(mux_insig[i]))
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continue;
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if (!op_outbit_to_outsig.count(mux_insig[i]))
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continue;
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auto op_outsig = op_outbit_to_outsig.at(mux_insig[i]);
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auto op_outsig = op_outbit_to_outsig.at(mux_insig[i]);
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if (op_mux_conn_map.count(op_outsig)) {
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remove_outsig(op_outsig);
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continue;
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}
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if (op_mux_conn_map.count(op_outsig)) {
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remove_outsig(op_outsig);
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continue;
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}
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int mux_port_id = i / mux_port_size;
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int mux_port_offset = i % mux_port_size;
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int mux_port_id = i / mux_port_size;
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int mux_port_offset = i % mux_port_size;
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int op_outsig_offset;
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for (op_outsig_offset = 0; op_outsig[op_outsig_offset] != mux_insig[i]; ++op_outsig_offset)
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;
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int op_outsig_offset;
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for (op_outsig_offset = 0; op_outsig[op_outsig_offset] != mux_insig[i]; ++op_outsig_offset)
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;
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int j = op_outsig_offset;
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do {
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if (!op_outbit_to_outsig.count(mux_insig[i]))
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break;
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int j = op_outsig_offset;
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do {
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if (!op_outbit_to_outsig.count(mux_insig[i]))
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break;
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if (op_outbit_to_outsig.at(mux_insig[i]) != op_outsig)
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break;
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if (op_outbit_to_outsig.at(mux_insig[i]) != op_outsig)
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break;
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++i;
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++j;
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} while ((i / mux_port_size == mux_port_id) && (j < op_outsig.size()));
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++i;
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++j;
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} while ((i / mux_port_size == mux_port_id) && (j < op_outsig.size()));
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int op_conn_width = j - op_outsig_offset;
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OpMuxConn inp = {
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op_outsig.extract(op_outsig_offset, op_conn_width),
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mux,
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outsig_to_operator.at(op_outsig),
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mux_port_id,
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mux_port_offset,
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op_outsig_offset,
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};
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int op_conn_width = j - op_outsig_offset;
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OpMuxConn inp = {
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op_outsig.extract(op_outsig_offset, op_conn_width),
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mux,
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outsig_to_operator.at(op_outsig),
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mux_port_id,
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mux_port_offset,
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op_outsig_offset,
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};
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op_mux_conn_map[op_outsig] = inp;
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op_mux_conn_map[op_outsig] = inp;
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--i;
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}
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};
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--i;
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}
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};
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std::function<void(RTLIL::SigSpec)> remove_connected_ops = [&](RTLIL::SigSpec sig) {
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auto mux_insig = assign_map(sig);
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@ -451,8 +443,8 @@ dict<RTLIL::SigSpec, OpMuxConn> find_valid_op_mux_conns(RTLIL::Module *module, d
|
|||
};
|
||||
|
||||
for (auto cell : module->cells()) {
|
||||
if (cell->type.in("$mux", "$_MUX_", "$pmux")) {
|
||||
remove_connected_ops(cell->getPort("\\S"));
|
||||
if (cell->type.in(ID($mux), ID($_MUX_), ID($pmux))) {
|
||||
remove_connected_ops(cell->getPort(ID(S)));
|
||||
find_op_mux_conns(cell);
|
||||
} else {
|
||||
for (auto &conn : cell->connections())
|
||||
|
|
@ -509,8 +501,8 @@ struct OptSharePass : public Pass {
|
|||
if (!cell_supported(cell))
|
||||
continue;
|
||||
|
||||
if (cell->type == "$alu") {
|
||||
for (RTLIL::IdString port_name : {"\\X", "\\CO"}) {
|
||||
if (cell->type == ID($alu)) {
|
||||
for (RTLIL::IdString port_name : {ID(X), ID(CO)}) {
|
||||
auto mux_insig = assign_map(cell->getPort(port_name));
|
||||
outsig_to_operator[mux_insig] = cell;
|
||||
for (auto outbit : mux_insig)
|
||||
|
|
@ -518,12 +510,12 @@ struct OptSharePass : public Pass {
|
|||
}
|
||||
}
|
||||
|
||||
auto mux_insig = assign_map(cell->getPort("\\Y"));
|
||||
auto mux_insig = assign_map(cell->getPort(ID(Y)));
|
||||
outsig_to_operator[mux_insig] = cell;
|
||||
for (auto outbit : mux_insig)
|
||||
op_outbit_to_outsig[outbit] = mux_insig;
|
||||
|
||||
for (RTLIL::IdString port_name : {"\\A", "\\B"}) {
|
||||
for (RTLIL::IdString port_name : {ID(A), ID(B)}) {
|
||||
auto op_insig = decode_port(cell, port_name, &assign_map);
|
||||
op_insigs.push_back(op_insig);
|
||||
operand_to_users[op_insig].insert(cell);
|
||||
|
|
@ -549,10 +541,10 @@ struct OptSharePass : public Pass {
|
|||
if (mux_port_conns.size() == 0) {
|
||||
int mux_port_num;
|
||||
|
||||
if (p.mux->type.in("$mux", "$_MUX_"))
|
||||
if (p.mux->type.in(ID($mux), ID($_MUX_)))
|
||||
mux_port_num = 2;
|
||||
else
|
||||
mux_port_num = p.mux->getPort("\\S").size();
|
||||
mux_port_num = p.mux->getPort(ID(S)).size();
|
||||
|
||||
mux_port_conns.resize(mux_port_num);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue