From 3d3479b0af0d2d59708a0828cfa785257c52d6fd Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Fri, 4 Oct 2019 10:57:47 +0200
Subject: [PATCH] Cleanup top modules and not used defines

---
 tests/anlogic/fsm.v     | 18 ------------------
 tests/anlogic/fsm.ys    |  6 +++---
 tests/anlogic/shifter.v |  6 ------
 tests/anlogic/tribuf.v  | 15 ---------------
 tests/anlogic/tribuf.ys |  4 ++--
 5 files changed, 5 insertions(+), 44 deletions(-)

diff --git a/tests/anlogic/fsm.v b/tests/anlogic/fsm.v
index 0605bd102..368fbaace 100644
--- a/tests/anlogic/fsm.v
+++ b/tests/anlogic/fsm.v
@@ -52,22 +52,4 @@
  endcase
  end
 
- endmodule
-
- module top (
-input clk,
-input rst,
-input a,
-input b,
-output g0,
-output g1
-);
-
-fsm u_fsm ( .clock(clk),
-            .reset(rst),
-            .req_0(a),
-            .req_1(b),
-            .gnt_0(g0),
-            .gnt_1(g1));
-
 endmodule
diff --git a/tests/anlogic/fsm.ys b/tests/anlogic/fsm.ys
index 6eb7b9a71..76a5d3e43 100644
--- a/tests/anlogic/fsm.ys
+++ b/tests/anlogic/fsm.ys
@@ -1,12 +1,12 @@
 read_verilog fsm.v
-hierarchy -top top
+hierarchy -top fsm
 proc
-flatten
+#flatten
 #ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
 #equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
 equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd fsm # Constrain all select calls below inside the top module
 select -assert-count 1 t:AL_MAP_LUT2
 select -assert-count 5 t:AL_MAP_LUT5
 select -assert-count 1 t:AL_MAP_LUT6
diff --git a/tests/anlogic/shifter.v b/tests/anlogic/shifter.v
index c55632552..04ae49d83 100644
--- a/tests/anlogic/shifter.v
+++ b/tests/anlogic/shifter.v
@@ -9,14 +9,8 @@ in
 
     always @(posedge clk)
 	begin
-`ifndef BUG
 		out    <= out >> 1;
 		out[7] <= in;
-`else
-
-		out    <= out << 1;
-		out[7] <= in;
-`endif
 	end
 
 endmodule
diff --git a/tests/anlogic/tribuf.v b/tests/anlogic/tribuf.v
index 870a02584..90dd314e4 100644
--- a/tests/anlogic/tribuf.v
+++ b/tests/anlogic/tribuf.v
@@ -6,18 +6,3 @@ module tristate (en, i, o);
 	assign o = en ? i : 1'bz;
 
 endmodule
-
-
-module top (
-input en,
-input a,
-output b
-);
-
-tristate u_tri (
-        .en (en ),
-        .i (a ),
-        .o (b )
-    );
-
-endmodule
diff --git a/tests/anlogic/tribuf.ys b/tests/anlogic/tribuf.ys
index 663e93fb2..0eb1338ac 100644
--- a/tests/anlogic/tribuf.ys
+++ b/tests/anlogic/tribuf.ys
@@ -1,9 +1,9 @@
 read_verilog tribuf.v
-hierarchy -top top
+hierarchy -top tristate
 proc
 flatten
 equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
-cd top # Constrain all select calls below inside the top module
+cd tristate # Constrain all select calls below inside the top module
 select -assert-count 1 t:$_TBUF_
 select -assert-none t:$_TBUF_ %% t:* %D