diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index b9957bd5e..289673e82 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -451,9 +451,8 @@ endmodule
 //-                 1 1 | y
 //-
 module \$_SR_NN_ (S, R, Q);
-parameter INIT = 1'bx;
 input S, R;
-output reg Q = INIT;
+output reg Q;
 always @(negedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -476,9 +475,8 @@ endmodule
 //-                 1 0 | y
 //-
 module \$_SR_NP_ (S, R, Q);
-parameter INIT = 1'bx;
 input S, R;
-output reg Q = INIT;
+output reg Q;
 always @(negedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -501,9 +499,8 @@ endmodule
 //-                 0 1 | y
 //-
 module \$_SR_PN_ (S, R, Q);
-parameter INIT = 1'bx;
 input S, R;
-output reg Q = INIT;
+output reg Q;
 always @(posedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -526,9 +523,8 @@ endmodule
 //-                 0 0 | y
 //-
 module \$_SR_PP_ (S, R, Q);
-parameter INIT = 1'bx;
 input S, R;
-output reg Q = INIT;
+output reg Q;
 always @(posedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -546,9 +542,8 @@ endmodule
 //- type is usually only used in netlists for formal verification.)
 //-
 module \$_FF_ (D, Q);
-parameter INIT = 1'bx;
 input D;
-output reg Q = INIT;
+output reg Q;
 always @($global_clock) begin
 	Q <= D;
 end
@@ -567,9 +562,8 @@ endmodule
 //-                 - - | q
 //-
 module \$_DFF_N_ (D, C, Q);
-parameter INIT = 1'bx;
 input D, C;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C) begin
 	Q <= D;
 end
@@ -587,9 +581,8 @@ endmodule
 //-                 - - | q
 //-
 module \$_DFF_P_ (D, C, Q);
-parameter INIT = 1'bx;
 input D, C;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C) begin
 	Q <= D;
 end
@@ -607,9 +600,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFFE_NN_ (D, C, E, Q);
-parameter INIT = 1'bx;
 input D, C, E;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C) begin
 	if (!E) Q <= D;
 end
@@ -627,9 +619,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFFE_NP_ (D, C, E, Q);
-parameter INIT = 1'bx;
 input D, C, E;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C) begin
 	if (E) Q <= D;
 end
@@ -647,9 +638,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFFE_PN_ (D, C, E, Q);
-parameter INIT = 1'bx;
 input D, C, E;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C) begin
 	if (!E) Q <= D;
 end
@@ -667,9 +657,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFFE_PP_ (D, C, E, Q);
-parameter INIT = 1'bx;
 input D, C, E;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C) begin
 	if (E) Q <= D;
 end
@@ -688,9 +677,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_NN0_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C or negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -712,9 +700,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_NN1_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C or negedge R) begin
 	if (R == 0)
 		Q <= 1;
@@ -736,9 +723,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_NP0_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C or posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -760,9 +746,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_NP1_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C or posedge R) begin
 	if (R == 1)
 		Q <= 1;
@@ -784,9 +769,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_PN0_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C or negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -808,9 +792,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_PN1_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C or negedge R) begin
 	if (R == 0)
 		Q <= 1;
@@ -832,9 +815,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_PP0_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C or posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -856,9 +838,8 @@ endmodule
 //-                 - - - | q
 //-
 module \$_DFF_PP1_ (D, C, R, Q);
-parameter INIT = 1'bx;
 input D, C, R;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C or posedge R) begin
 	if (R == 1)
 		Q <= 1;
@@ -881,9 +862,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_NNN_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C, negedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -909,9 +889,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_NNP_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C, negedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -937,9 +916,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_NPN_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C, posedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -964,9 +942,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_NPP_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(negedge C, posedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -991,9 +968,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_PNN_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C, negedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -1019,9 +995,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_PNP_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C, negedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -1047,9 +1022,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_PPN_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C, posedge S, negedge R) begin
 	if (R == 0)
 		Q <= 0;
@@ -1074,9 +1048,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DFFSR_PPP_ (C, S, R, D, Q);
-parameter INIT = 1'bx;
 input C, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @(posedge C, posedge S, posedge R) begin
 	if (R == 1)
 		Q <= 0;
@@ -1099,9 +1072,8 @@ endmodule
 //-                 - - | q
 //-
 module \$_DLATCH_N_ (E, D, Q);
-parameter INIT = 1'bx;
 input E, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (E == 0)
 		Q <= D;
@@ -1120,9 +1092,8 @@ endmodule
 //-                 - - | q
 //-
 module \$_DLATCH_P_ (E, D, Q);
-parameter INIT = 1'bx;
 input E, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (E == 1)
 		Q <= D;
@@ -1143,9 +1114,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_NNN_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 0)
 		Q <= 0;
@@ -1171,9 +1141,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_NNP_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 1)
 		Q <= 0;
@@ -1199,9 +1168,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_NPN_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 0)
 		Q <= 0;
@@ -1226,9 +1194,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_NPP_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 1)
 		Q <= 0;
@@ -1253,9 +1220,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_PNN_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 0)
 		Q <= 0;
@@ -1281,9 +1247,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_PNP_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 1)
 		Q <= 0;
@@ -1309,9 +1274,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_PPN_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 0)
 		Q <= 0;
@@ -1336,9 +1300,8 @@ endmodule
 //-                 - - - - | q
 //-
 module \$_DLATCHSR_PPP_ (E, S, R, D, Q);
-parameter INIT = 1'bx;
 input E, S, R, D;
-output reg Q = INIT;
+output reg Q;
 always @* begin
 	if (R == 1)
 		Q <= 0;
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index a1e0c1575..8e43fe058 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1464,11 +1464,10 @@ module \$dff (CLK, D, Q);
 
 parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
-parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q = INIT;
+output reg [WIDTH-1:0] Q;
 wire pos_clk = CLK == CLK_POLARITY;
 
 always @(posedge pos_clk) begin
@@ -1484,11 +1483,10 @@ module \$dffe (CLK, EN, D, Q);
 parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter EN_POLARITY = 1'b1;
-parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK, EN;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q = INIT;
+output reg [WIDTH-1:0] Q;
 wire pos_clk = CLK == CLK_POLARITY;
 
 always @(posedge pos_clk) begin
@@ -1506,11 +1504,10 @@ parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter SET_POLARITY = 1'b1;
 parameter CLR_POLARITY = 1'b1;
-parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK;
 input [WIDTH-1:0] SET, CLR, D;
-output reg [WIDTH-1:0] Q = INIT;
+output reg [WIDTH-1:0] Q;
 
 wire pos_clk = CLK == CLK_POLARITY;
 wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;
@@ -1540,11 +1537,10 @@ parameter WIDTH = 0;
 parameter CLK_POLARITY = 1'b1;
 parameter ARST_POLARITY = 1'b1;
 parameter ARST_VALUE = 0;
-parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input CLK, ARST;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q = INIT;
+output reg [WIDTH-1:0] Q;
 wire pos_clk = CLK == CLK_POLARITY;
 wire pos_arst = ARST == ARST_POLARITY;
 
@@ -1563,11 +1559,10 @@ module \$dlatch (EN, D, Q);
 
 parameter WIDTH = 0;
 parameter EN_POLARITY = 1'b1;
-parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input EN;
 input [WIDTH-1:0] D;
-output reg [WIDTH-1:0] Q = INIT;
+output reg [WIDTH-1:0] Q;
 
 always @* begin
 	if (EN == EN_POLARITY)
@@ -1585,11 +1580,10 @@ parameter WIDTH = 0;
 parameter EN_POLARITY = 1'b1;
 parameter SET_POLARITY = 1'b1;
 parameter CLR_POLARITY = 1'b1;
-parameter INIT = {WIDTH > 0 ? WIDTH : 1{1'bx}};
 
 input EN;
 input [WIDTH-1:0] SET, CLR, D;
-output reg [WIDTH-1:0] Q = INIT;
+output reg [WIDTH-1:0] Q;
 
 wire pos_en = EN == EN_POLARITY;
 wire [WIDTH-1:0] pos_set = SET_POLARITY ? SET : ~SET;