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iopadmap: fixes as suggested by @mwkmwkmwk

This commit is contained in:
Eddie Hung 2020-02-13 14:57:06 -08:00
parent ebb11bcea4
commit 3d2a2e8799
1 changed files with 11 additions and 19 deletions
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30
passes/techmap/iopadmap.cc
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@ -408,35 +408,27 @@ struct IopadmapPass : public Pass {
RTLIL::Wire *wire = it.first; RTLIL::Wire *wire = it.first;
RTLIL::Wire *new_wire = module->addWire(NEW_ID, wire); RTLIL::Wire *new_wire = module->addWire(NEW_ID, wire);
module->swap_names(new_wire, wire); module->swap_names(new_wire, wire);
wire->attributes.clear();
for (int i = 0; i < wire->width; i++) for (int i = 0; i < wire->width; i++)
{ {
SigBit wire_bit(wire, i); SigBit wire_bit(wire, i);
if (!it.second.count(i)) { if (!it.second.count(i)) {
if (wire->port_output) { if (wire->port_output)
module->connect(SigSpec(new_wire, i), SigSpec(wire, i)); module->connect(SigSpec(new_wire, i), SigSpec(wire, i));
wire->attributes.clear(); else
}
else {
module->connect(SigSpec(wire, i), SigSpec(new_wire, i)); module->connect(SigSpec(wire, i), SigSpec(new_wire, i));
wire->attributes.clear();
}
} else { } else {
auto &new_conn = it.second.at(i); auto &new_conn = it.second.at(i);
new_conn.first->setPort(new_conn.second, RTLIL::SigSpec(new_wire, i)); new_conn.first->setPort(new_conn.second, RTLIL::SigSpec(new_wire, i));
}
}
// For cell outputs, move \init attributes from old wire to new wire if (wire->port_output) {
if (new_conn.first->output(new_conn.second)) { auto jt = new_wire->attributes.find(ID(init));
auto it = wire->attributes.find(ID(init)); // For output ports, move \init attributes from old wire to new wire
if (it != wire->attributes.end()) { if (jt != new_wire->attributes.end()) {
for (auto it2 = wire->attributes.begin(); it2 != wire->attributes.end(); ) wire->attributes[ID(init)] = std::move(jt->second);
if (it == it2) new_wire->attributes.erase(jt);
++it2;
else
it2 = wire->attributes.erase(it2);
new_wire->attributes.erase(ID(init));
}
}
} }
} }