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Merge remote-tracking branch 'origin/xaig' into xc7mux

This commit is contained in:
Eddie Hung 2019-06-18 09:51:28 -07:00
parent 2b0e28b261 b304744d15
commit 3d283e69f8
2 changed files with 37 additions and 37 deletions
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10
techlibs/ecp5/cells_map.v
View File

@ -70,6 +70,8 @@ module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
// Need to swap input ordering, and fix init accordingly,
// to match ABC's expectation of LUT inputs in non-decreasing
@ -86,19 +88,15 @@ module \$lut (A, Y);
endfunction
function [2**P_WIDTH-1:0] permute_init;
input [2**P_WIDTH-1:0] orig;
integer i;
begin
permute_init = 0;
for (i = 0; i < 2**P_WIDTH; i = i + 1)
permute_init[i] = orig[permute_index(i)];
permute_init[i] = LUT[permute_index(i)];
end
endfunction
parameter [2**P_WIDTH-1:0] P_LUT = permute_init(LUT);
input [WIDTH-1:0] A;
output Y;
parameter [2**P_WIDTH-1:0] P_LUT = permute_init();
generate
if (WIDTH == 1) begin

64
techlibs/xilinx/lut_map.v
View File

@ -29,30 +29,32 @@ module \$lut (A, Y);
input [WIDTH-1:0] A;
output Y;
// Need to swap input ordering, and fix init accordingly,
// Need to swap input ordering of wide LUTs, and fix init accordingly,
// to match ABC's expectation of LUT inputs in non-decreasing
// delay order
function [WIDTH-1:0] permute_index;
input [WIDTH-1:0] i;
integer j;
begin
permute_index = 0;
for (j = 0; j < WIDTH; j = j + 1)
permute_index[WIDTH-1 - j] = i[j];
if (WIDTH == 7)
permute_index = { i[5:0], i[6] };
else if (WIDTH == 8)
permute_index = { i[5:0], i[6], i[7] };
else
permute_index = i;
end
endfunction
function [2**WIDTH-1:0] permute_init;
input [2**WIDTH-1:0] orig;
integer i;
begin
permute_init = 0;
for (i = 0; i < 2**WIDTH; i = i + 1)
permute_init[i] = orig[permute_index(i)];
permute_init[i] = LUT[permute_index(i)];
end
endfunction
parameter [2**WIDTH-1:0] P_LUT = permute_init(LUT);
parameter [2**WIDTH-1:0] P_LUT = permute_init();
generate
if (WIDTH == 1) begin
@ -61,54 +63,54 @@ module \$lut (A, Y);
end else
if (WIDTH == 2) begin
LUT2 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[1]), .I1(A[0]));
.I0(A[0]), .I1(A[1]));
end else
if (WIDTH == 3) begin
LUT3 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[2]), .I1(A[1]), .I2(A[0]));
.I0(A[0]), .I1(A[1]), .I2(A[2]));
end else
if (WIDTH == 4) begin
LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[3]), .I1(A[2]), .I2(A[1]),
.I3(A[0]));
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]));
end else
if (WIDTH == 5) begin
LUT5 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[4]), .I1(A[3]), .I2(A[2]),
.I3(A[1]), .I4(A[0]));
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]));
end else
if (WIDTH == 6) begin
LUT6 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
.I0(A[5]), .I1(A[4]), .I2(A[3]),
.I3(A[2]), .I4(A[1]), .I5(A[0]));
.I0(A[0]), .I1(A[1]), .I2(A[2]),
.I3(A[3]), .I4(A[4]), .I5(A[5]));
end else
if (WIDTH == 7) begin
wire T0, T1;
LUT6 #(.INIT(P_LUT[63:0])) fpga_lut_0 (.O(T0),
.I0(A[5]), .I1(A[4]), .I2(A[3]),
.I3(A[2]), .I4(A[1]), .I5(A[0]));
.I0(A[1]), .I1(A[2]), .I2(A[3]),
.I3(A[4]), .I4(A[5]), .I5(A[6]));
LUT6 #(.INIT(P_LUT[127:64])) fpga_lut_1 (.O(T1),
.I0(A[5]), .I1(A[4]), .I2(A[3]),
.I3(A[2]), .I4(A[1]), .I5(A[0]));
MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6]));
.I0(A[1]), .I1(A[2]), .I2(A[3]),
.I3(A[4]), .I4(A[5]), .I5(A[6]));
MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[0]));
end else
if (WIDTH == 8) begin
wire T0, T1, T2, T3, T4, T5;
LUT6 #(.INIT(P_LUT[63:0])) fpga_lut_0 (.O(T0),
.I0(A[5]), .I1(A[4]), .I2(A[3]),
.I3(A[2]), .I4(A[1]), .I5(A[0]));
.I0(A[2]), .I1(A[3]), .I2(A[4]),
.I3(A[5]), .I4(A[6]), .I5(A[7]));
LUT6 #(.INIT(P_LUT[127:64])) fpga_lut_1 (.O(T1),
.I0(A[5]), .I1(A[4]), .I2(A[3]),
.I3(A[2]), .I4(A[1]), .I5(A[0]));
.I0(A[2]), .I1(A[3]), .I2(A[4]),
.I3(A[5]), .I4(A[6]), .I5(A[7]));
LUT6 #(.INIT(P_LUT[191:128])) fpga_lut_2 (.O(T2),
.I0(A[5]), .I1(A[4]), .I2(A[3]),
.I3(A[2]), .I4(A[1]), .I5(A[0]));
.I0(A[2]), .I1(A[3]), .I2(A[4]),
.I3(A[5]), .I4(A[6]), .I5(A[7]));
LUT6 #(.INIT(P_LUT[255:192])) fpga_lut_3 (.O(T3),
.I0(A[5]), .I1(A[4]), .I2(A[3]),
.I3(A[2]), .I4(A[1]), .I5(A[0]));
MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6]));
MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6]));
MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7]));
.I0(A[2]), .I1(A[3]), .I2(A[4]),
.I3(A[5]), .I4(A[6]), .I5(A[7]));
MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[1]));
MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[1]));
MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[0]));
end else begin
wire _TECHMAP_FAIL_ = 1;
end