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intel_alm: work around a Quartus ICE

This commit is contained in:
Dan Ravensloft 2020-04-23 00:56:49 +01:00 committed by Marcelina Kościelnicka
parent b700592881
commit 3d149aff73
2 changed files with 22 additions and 0 deletions
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10
techlibs/intel_alm/synth_intel_alm.cc
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@ -200,6 +200,8 @@ struct SynthIntelALMPass : public ScriptPass {
if (check_label("map_ffs")) {
run("dff2dffe -direct-match $_DFF_*");
// As mentioned in common/dff_sim.v, Intel flops power up to zero,
// so use `zinit` to add inverters where needed.
run("zinit");
run("techmap -map +/techmap.v -map +/intel_alm/common/dff_map.v");
run("opt -full -undriven -mux_undef");
@ -223,8 +225,16 @@ struct SynthIntelALMPass : public ScriptPass {
if (check_label("quartus")) {
if (quartus || help_mode) {
// Quartus ICEs if you have a wire which has `[]` in its name,
// which Yosys produces when building memories out of flops.
run("rename -hide w:*[* w:*]*");
// VQM mode does not support 'x, so replace those with zero.
run("setundef -zero");
// VQM mode does not support multi-bit constant assignments
// (e.g. 2'b00 is an error), so as a workaround use references
// to constant driver cells, which Quartus accepts.
run("hilomap -singleton -hicell __MISTRAL_VCC Q -locell __MISTRAL_GND Q");
// Rename from Yosys-internal MISTRAL_* cells to Quartus cells.
run("techmap -map +/intel_alm/common/quartus_rename.v");
run(stringf("techmap -map +/intel_alm/%s/quartus_rename.v", family_opt.c_str()));
}

12
tests/arch/intel_alm/quartus_ice.ys Normal file
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@ -0,0 +1,12 @@
read_verilog <<EOT
// Verilog has syntax for raw identifiers, where you start it with \ and end it with a space.
// This test crashes Quartus due to it parsing \a[10] as a wire slice and not a raw identifier.
module top();
(* keep *) wire [31:0] \a[10] ;
(* keep *) wire b;
assign b = \a[10] [31];
endmodule
EOT
synth_intel_alm -family cyclonev -quartus
select -assert-none w:*[* w:*]*