mirror of https://github.com/YosysHQ/yosys.git
Merge remote-tracking branch 'origin/eddie/muxpack' into xc7mux_wip
This commit is contained in:
Eddie Hung
commit
3cf2afc280
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|
@ -25,6 +25,7 @@ Yosys 0.8 .. Yosys 0.8-dev
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- Extended "muxcover -mux{4,8,16}=<cost>"
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- Fixed sign extension of unsized constants with 'bx and 'bz MSB
|
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- Added "synth -abc9" (experimental)
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- Added "muxpack" pass
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- "synth_xilinx" to now infer wide multiplexers (-nomux to disable)
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|
|
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@ -14,5 +14,6 @@ OBJS += passes/opt/opt_demorgan.o
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OBJS += passes/opt/rmports.o
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OBJS += passes/opt/opt_lut.o
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OBJS += passes/opt/pmux2shiftx.o
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OBJS += passes/opt/muxpack.o
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endif
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|
|
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|
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@ -0,0 +1,337 @@
|
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/*
|
||||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
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* 2019 Eddie Hung <eddie@fpgeh.com>
|
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*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
*/
|
||||
|
||||
#include "kernel/yosys.h"
|
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#include "kernel/sigtools.h"
|
||||
|
||||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
struct ExclusiveDatabase
|
||||
{
|
||||
Module *module;
|
||||
const SigMap &sigmap;
|
||||
|
||||
dict<SigBit, SigSpec> sig_cmp_prev;
|
||||
dict<SigSpec, pool<SigSpec>> sig_exclusive;
|
||||
|
||||
ExclusiveDatabase(Module *module, const SigMap &sigmap) : module(module), sigmap(sigmap)
|
||||
{
|
||||
SigSpec a_port, b_port, y_port;
|
||||
for (auto cell : module->cells()) {
|
||||
if (cell->type == "$eq") {
|
||||
a_port = sigmap(cell->getPort("\\A"));
|
||||
b_port = sigmap(cell->getPort("\\B"));
|
||||
if (!b_port.is_fully_const()) {
|
||||
if (!a_port.is_fully_const())
|
||||
continue;
|
||||
std::swap(a_port, b_port);
|
||||
}
|
||||
y_port = sigmap(cell->getPort("\\Y"));
|
||||
}
|
||||
else if (cell->type == "$logic_not") {
|
||||
a_port = sigmap(cell->getPort("\\A"));
|
||||
b_port = Const(RTLIL::S0, GetSize(a_port));
|
||||
y_port = sigmap(cell->getPort("\\Y"));
|
||||
}
|
||||
else continue;
|
||||
|
||||
auto r = sig_exclusive[a_port].insert(b_port.as_const());
|
||||
if (!r.second)
|
||||
continue;
|
||||
sig_cmp_prev[y_port] = a_port;
|
||||
}
|
||||
}
|
||||
|
||||
bool query(const SigSpec& sig1, const SigSpec& sig2) const
|
||||
{
|
||||
// FIXME: O(N^2)
|
||||
for (auto bit1 : sig1.bits()) {
|
||||
auto it = sig_cmp_prev.find(bit1);
|
||||
if (it == sig_cmp_prev.end())
|
||||
return false;
|
||||
|
||||
for (auto bit2 : sig2.bits()) {
|
||||
auto jt = sig_cmp_prev.find(bit2);
|
||||
if (jt == sig_cmp_prev.end())
|
||||
return false;
|
||||
|
||||
if (it->second != jt->second)
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
};
|
||||
|
||||
|
||||
struct MuxpackWorker
|
||||
{
|
||||
Module *module;
|
||||
SigMap sigmap;
|
||||
|
||||
int mux_count, pmux_count;
|
||||
|
||||
pool<Cell*> remove_cells;
|
||||
|
||||
dict<SigSpec, Cell*> sig_chain_next;
|
||||
dict<SigSpec, Cell*> sig_chain_prev;
|
||||
pool<SigBit> sigbit_with_non_chain_users;
|
||||
pool<Cell*> chain_start_cells;
|
||||
pool<Cell*> candidate_cells;
|
||||
|
||||
ExclusiveDatabase excl_db;
|
||||
|
||||
void make_sig_chain_next_prev()
|
||||
{
|
||||
for (auto wire : module->wires())
|
||||
{
|
||||
if (wire->port_output || wire->get_bool_attribute("\\keep")) {
|
||||
for (auto bit : sigmap(wire))
|
||||
sigbit_with_non_chain_users.insert(bit);
|
||||
}
|
||||
}
|
||||
|
||||
for (auto cell : module->cells())
|
||||
{
|
||||
if (cell->type.in("$mux", "$pmux") && !cell->get_bool_attribute("\\keep"))
|
||||
{
|
||||
SigSpec a_sig = sigmap(cell->getPort("\\A"));
|
||||
SigSpec b_sig;
|
||||
if (cell->type == "$mux")
|
||||
b_sig = sigmap(cell->getPort("\\B"));
|
||||
SigSpec y_sig = sigmap(cell->getPort("\\Y"));
|
||||
|
||||
if (sig_chain_next.count(a_sig))
|
||||
for (auto a_bit : a_sig.bits())
|
||||
sigbit_with_non_chain_users.insert(a_bit);
|
||||
else {
|
||||
sig_chain_next[a_sig] = cell;
|
||||
candidate_cells.insert(cell);
|
||||
}
|
||||
|
||||
if (!b_sig.empty()) {
|
||||
if (sig_chain_next.count(b_sig))
|
||||
for (auto b_bit : b_sig.bits())
|
||||
sigbit_with_non_chain_users.insert(b_bit);
|
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else {
|
||||
sig_chain_next[b_sig] = cell;
|
||||
candidate_cells.insert(cell);
|
||||
}
|
||||
}
|
||||
|
||||
sig_chain_prev[y_sig] = cell;
|
||||
continue;
|
||||
}
|
||||
|
||||
for (auto conn : cell->connections())
|
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if (cell->input(conn.first))
|
||||
for (auto bit : sigmap(conn.second))
|
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sigbit_with_non_chain_users.insert(bit);
|
||||
}
|
||||
}
|
||||
|
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void find_chain_start_cells()
|
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{
|
||||
for (auto cell : candidate_cells)
|
||||
{
|
||||
log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
|
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|
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SigSpec a_sig = sigmap(cell->getPort("\\A"));
|
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if (cell->type == "$mux") {
|
||||
SigSpec b_sig = sigmap(cell->getPort("\\B"));
|
||||
if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1)
|
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goto start_cell;
|
||||
|
||||
if (!sig_chain_prev.count(a_sig))
|
||||
a_sig = b_sig;
|
||||
}
|
||||
else if (cell->type == "$pmux") {
|
||||
if (!sig_chain_prev.count(a_sig))
|
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goto start_cell;
|
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}
|
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else log_abort();
|
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|
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for (auto bit : a_sig.bits())
|
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if (sigbit_with_non_chain_users.count(bit))
|
||||
goto start_cell;
|
||||
|
||||
{
|
||||
Cell *prev_cell = sig_chain_prev.at(a_sig);
|
||||
log_assert(prev_cell);
|
||||
SigSpec s_sig = sigmap(cell->getPort("\\S"));
|
||||
SigSpec next_s_sig = sigmap(prev_cell->getPort("\\S"));
|
||||
if (!excl_db.query(s_sig, next_s_sig))
|
||||
goto start_cell;
|
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}
|
||||
|
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continue;
|
||||
|
||||
start_cell:
|
||||
chain_start_cells.insert(cell);
|
||||
}
|
||||
}
|
||||
|
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vector<Cell*> create_chain(Cell *start_cell)
|
||||
{
|
||||
vector<Cell*> chain;
|
||||
|
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Cell *c = start_cell;
|
||||
while (c != nullptr)
|
||||
{
|
||||
chain.push_back(c);
|
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|
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SigSpec y_sig = sigmap(c->getPort("\\Y"));
|
||||
|
||||
if (sig_chain_next.count(y_sig) == 0)
|
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break;
|
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|
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c = sig_chain_next.at(y_sig);
|
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if (chain_start_cells.count(c) != 0)
|
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break;
|
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}
|
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|
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return chain;
|
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}
|
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|
||||
void process_chain(vector<Cell*> &chain)
|
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{
|
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if (GetSize(chain) < 2)
|
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return;
|
||||
|
||||
int cursor = 0;
|
||||
while (cursor < GetSize(chain))
|
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{
|
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int cases = GetSize(chain) - cursor;
|
||||
|
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Cell *first_cell = chain[cursor];
|
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dict<int, SigBit> taps_dict;
|
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|
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if (cases < 2) {
|
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cursor++;
|
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continue;
|
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}
|
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|
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Cell *last_cell = chain[cursor+cases-1];
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|
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log("Converting %s.%s ... %s.%s to a pmux with %d cases.\n",
|
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log_id(module), log_id(first_cell), log_id(module), log_id(last_cell), cases);
|
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|
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mux_count += cases;
|
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pmux_count += 1;
|
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|
||||
first_cell->type = "$pmux";
|
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SigSpec b_sig = first_cell->getPort("\\B");
|
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SigSpec s_sig = first_cell->getPort("\\S");
|
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|
||||
for (int i = 1; i < cases; i++) {
|
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Cell* prev_cell = chain[cursor+i-1];
|
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Cell* cursor_cell = chain[cursor+i];
|
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if (sigmap(prev_cell->getPort("\\Y")) == sigmap(cursor_cell->getPort("\\A"))) {
|
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b_sig.append(cursor_cell->getPort("\\B"));
|
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s_sig.append(cursor_cell->getPort("\\S"));
|
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}
|
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else {
|
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log_assert(cursor_cell->type == "$mux");
|
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b_sig.append(cursor_cell->getPort("\\A"));
|
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s_sig.append(module->LogicNot(NEW_ID, cursor_cell->getPort("\\S")));
|
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}
|
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remove_cells.insert(cursor_cell);
|
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}
|
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|
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first_cell->setPort("\\B", b_sig);
|
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first_cell->setPort("\\S", s_sig);
|
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first_cell->setParam("\\S_WIDTH", GetSize(s_sig));
|
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first_cell->setPort("\\Y", last_cell->getPort("\\Y"));
|
||||
|
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cursor += cases;
|
||||
}
|
||||
}
|
||||
|
||||
void cleanup()
|
||||
{
|
||||
for (auto cell : remove_cells)
|
||||
module->remove(cell);
|
||||
|
||||
remove_cells.clear();
|
||||
sig_chain_next.clear();
|
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sig_chain_prev.clear();
|
||||
chain_start_cells.clear();
|
||||
candidate_cells.clear();
|
||||
}
|
||||
|
||||
MuxpackWorker(Module *module) :
|
||||
module(module), sigmap(module), mux_count(0), pmux_count(0), excl_db(module, sigmap)
|
||||
{
|
||||
make_sig_chain_next_prev();
|
||||
find_chain_start_cells();
|
||||
|
||||
for (auto c : chain_start_cells) {
|
||||
vector<Cell*> chain = create_chain(c);
|
||||
process_chain(chain);
|
||||
}
|
||||
|
||||
cleanup();
|
||||
}
|
||||
};
|
||||
|
||||
struct MuxpackPass : public Pass {
|
||||
MuxpackPass() : Pass("muxpack", "$mux/$pmux cascades to $pmux") { }
|
||||
void help() YS_OVERRIDE
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" muxpack [selection]\n");
|
||||
log("\n");
|
||||
log("This pass converts cascaded chains of $pmux cells (e.g. those create from case\n");
|
||||
log("constructs) and $mux cells (e.g. those created by if-else constructs) into\n");
|
||||
log("$pmux cells.\n");
|
||||
log("\n");
|
||||
log("This optimisation is conservative --- it will only pack $mux or $pmux cells with\n");
|
||||
log("other such cells if it can be certain that the select lines are mutually\n");
|
||||
log("exclusive.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
log_header(design, "Executing MUXPACK pass ($mux cell cascades to $pmux).\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
{
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
int mux_count = 0;
|
||||
int pmux_count = 0;
|
||||
|
||||
for (auto module : design->selected_modules()) {
|
||||
MuxpackWorker worker(module);
|
||||
mux_count += worker.mux_count;
|
||||
pmux_count += worker.pmux_count;
|
||||
}
|
||||
|
||||
log("Converted %d (p)mux cells into %d pmux cells.\n", mux_count, pmux_count);
|
||||
}
|
||||
} MuxpackPass;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
module mux_if_unbal_4_1 #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @*
|
||||
if (s == 0) o <= i[0*W+:W];
|
||||
else if (s == 1) o <= i[1*W+:W];
|
||||
else if (s == 2) o <= i[2*W+:W];
|
||||
else if (s == 3) o <= i[3*W+:W];
|
||||
else o <= {W{1'bx}};
|
||||
endmodule
|
||||
|
||||
module mux_if_unbal_5_3 #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @* begin
|
||||
o <= {W{1'bx}};
|
||||
if (s == 0) o <= i[0*W+:W];
|
||||
if (s == 1) o <= i[1*W+:W];
|
||||
if (s == 2) o <= i[2*W+:W];
|
||||
if (s == 3) o <= i[3*W+:W];
|
||||
if (s == 4) o <= i[4*W+:W];
|
||||
end
|
||||
endmodule
|
||||
|
||||
module mux_if_unbal_5_3_invert #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @*
|
||||
if (s != 0)
|
||||
if (s != 1)
|
||||
if (s != 2)
|
||||
if (s != 3)
|
||||
if (s != 4) o <= i[4*W+:W];
|
||||
else o <= i[0*W+:W];
|
||||
else o <= i[3*W+:W];
|
||||
else o <= i[2*W+:W];
|
||||
else o <= i[1*W+:W];
|
||||
else o <= {W{1'bx}};
|
||||
endmodule
|
||||
|
||||
module mux_if_unbal_5_3_width_mismatch #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @* begin
|
||||
o <= {W{1'bx}};
|
||||
if (s == 0) o <= i[0*W+:W];
|
||||
if (s == 1) o <= i[1*W+:W];
|
||||
if (s == 2) o[W-2:0] <= i[2*W+:W-1];
|
||||
if (s == 3) o <= i[3*W+:W];
|
||||
if (s == 4) o <= i[4*W+:W];
|
||||
end
|
||||
endmodule
|
||||
|
||||
module mux_if_unbal_4_1_missing #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @* begin
|
||||
if (s == 0) o <= i[0*W+:W];
|
||||
// else if (s == 1) o <= i[1*W+:W];
|
||||
// else if (s == 2) o <= i[2*W+:W];
|
||||
else if (s == 3) o <= i[3*W+:W];
|
||||
else o <= {W{1'bx}};
|
||||
end
|
||||
endmodule
|
||||
|
||||
module mux_if_unbal_5_3_order #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @* begin
|
||||
o <= {W{1'bx}};
|
||||
if (s == 3) o <= i[3*W+:W];
|
||||
if (s == 2) o <= i[2*W+:W];
|
||||
if (s == 1) o <= i[1*W+:W];
|
||||
if (s == 4) o <= i[4*W+:W];
|
||||
if (s == 0) o <= i[0*W+:W];
|
||||
end
|
||||
endmodule
|
||||
|
||||
module mux_if_unbal_4_1_nonexcl #(parameter N=4, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @*
|
||||
if (s == 0) o <= i[0*W+:W];
|
||||
else if (s == 1) o <= i[1*W+:W];
|
||||
else if (s == 2) o <= i[2*W+:W];
|
||||
else if (s == 3) o <= i[3*W+:W];
|
||||
else if (s == 0) o <= {W{1'b0}};
|
||||
else o <= {W{1'bx}};
|
||||
endmodule
|
||||
|
||||
module mux_if_unbal_5_3_nonexcl #(parameter N=5, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @* begin
|
||||
o <= {W{1'bx}};
|
||||
if (s == 0) o <= i[0*W+:W];
|
||||
if (s == 1) o <= i[1*W+:W];
|
||||
if (s == 2) o <= i[2*W+:W];
|
||||
if (s == 3) o <= i[3*W+:W];
|
||||
if (s == 4) o <= i[4*W+:W];
|
||||
if (s == 0) o <= i[2*W+:W];
|
||||
end
|
||||
endmodule
|
||||
|
||||
module mux_case_unbal_8_7#(parameter N=8, parameter W=7) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @* begin
|
||||
o <= {W{1'bx}};
|
||||
case (s)
|
||||
0: o <= i[0*W+:W];
|
||||
default:
|
||||
case (s)
|
||||
1: o <= i[1*W+:W];
|
||||
2: o <= i[2*W+:W];
|
||||
default:
|
||||
case (s)
|
||||
3: o <= i[3*W+:W];
|
||||
4: o <= i[4*W+:W];
|
||||
5: o <= i[5*W+:W];
|
||||
default:
|
||||
case (s)
|
||||
6: o <= i[6*W+:W];
|
||||
default: o <= i[7*W+:W];
|
||||
endcase
|
||||
endcase
|
||||
endcase
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
||||
module mux_if_bal_8_2 #(parameter N=8, parameter W=2) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @*
|
||||
if (s[0] == 1'b0)
|
||||
if (s[1] == 1'b0)
|
||||
if (s[2] == 1'b0)
|
||||
o <= i[0*W+:W];
|
||||
else
|
||||
o <= i[1*W+:W];
|
||||
else
|
||||
if (s[2] == 1'b0)
|
||||
o <= i[2*W+:W];
|
||||
else
|
||||
o <= i[3*W+:W];
|
||||
else
|
||||
if (s[1] == 1'b0)
|
||||
if (s[2] == 1'b0)
|
||||
o <= i[4*W+:W];
|
||||
else
|
||||
o <= i[5*W+:W];
|
||||
else
|
||||
if (s[2] == 1'b0)
|
||||
o <= i[6*W+:W];
|
||||
else
|
||||
o <= i[7*W+:W];
|
||||
endmodule
|
||||
|
||||
module mux_if_bal_5_1 #(parameter N=5, parameter W=1) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output reg [W-1:0] o);
|
||||
always @*
|
||||
if (s[0] == 1'b0)
|
||||
if (s[1] == 1'b0)
|
||||
if (s[2] == 1'b0)
|
||||
o <= i[0*W+:W];
|
||||
else
|
||||
o <= i[1*W+:W];
|
||||
else
|
||||
if (s[2] == 1'b0)
|
||||
o <= i[2*W+:W];
|
||||
else
|
||||
o <= i[3*W+:W];
|
||||
else
|
||||
o <= i[4*W+:W];
|
||||
endmodule
|
||||
|
||||
module cliffordwolf_nonexclusive_select (
|
||||
input wire x, y, z,
|
||||
input wire a, b, c, d,
|
||||
output reg o
|
||||
);
|
||||
always @* begin
|
||||
o = a;
|
||||
if (x) o = b;
|
||||
if (y) o = c;
|
||||
if (z) o = d;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module cliffordwolf_freduce (
|
||||
input wire [1:0] s,
|
||||
input wire a, b, c, d,
|
||||
output reg [3:0] o
|
||||
);
|
||||
always @* begin
|
||||
o = {4{a}};
|
||||
if (s == 0) o = {3{b}};
|
||||
if (s == 1) o = {2{c}};
|
||||
if (s == 2) o = d;
|
||||
end
|
||||
endmodule
|
||||
|
||||
module case_nonexclusive_select (
|
||||
input wire [1:0] x, y,
|
||||
input wire a, b, c, d, e,
|
||||
output reg o
|
||||
);
|
||||
always @* begin
|
||||
case (x)
|
||||
0, 2: o = b;
|
||||
1: o = c;
|
||||
default: begin
|
||||
o = a;
|
||||
if (y == 0) o = d;
|
||||
if (y == 1) o = e;
|
||||
end
|
||||
endcase
|
||||
end
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,214 @@
|
|||
read_verilog muxpack.v
|
||||
design -save read
|
||||
|
||||
hierarchy -top mux_if_unbal_4_1
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_if_unbal_5_3
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
# TODO: Currently ExclusiveDatabase only analyses $eq cells
|
||||
#design -load read
|
||||
#hierarchy -top mux_if_unbal_5_3_invert
|
||||
#prep
|
||||
#design -save gold
|
||||
#muxpack
|
||||
#opt
|
||||
#stat
|
||||
#select -assert-count 0 t:$mux
|
||||
#select -assert-count 1 t:$pmux
|
||||
#design -stash gate
|
||||
#design -import gold -as gold
|
||||
#design -import gate -as gate
|
||||
#miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
#sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_if_unbal_5_3_width_mismatch
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 2 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_if_unbal_4_1_missing
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_if_unbal_5_3_order
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_if_unbal_4_1_nonexcl
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_if_unbal_5_3_nonexcl
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_case_unbal_8_7
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 1 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_if_bal_8_2
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 7 t:$mux
|
||||
select -assert-count 0 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top mux_if_bal_5_1
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 4 t:$mux
|
||||
select -assert-count 0 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top cliffordwolf_nonexclusive_select
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 3 t:$mux
|
||||
select -assert-count 0 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
#design -load read
|
||||
#hierarchy -top cliffordwolf_freduce
|
||||
#prep
|
||||
#design -save gold
|
||||
#proc; opt; freduce; opt
|
||||
#show
|
||||
#muxpack
|
||||
#opt
|
||||
#stat
|
||||
#select -assert-count 0 t:$mux
|
||||
#select -assert-count 1 t:$pmux
|
||||
#design -stash gate
|
||||
#design -import gold -as gold
|
||||
#design -import gate -as gate
|
||||
#miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
#sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
design -load read
|
||||
hierarchy -top case_nonexclusive_select
|
||||
prep
|
||||
design -save gold
|
||||
muxpack
|
||||
opt
|
||||
stat
|
||||
select -assert-count 0 t:$mux
|
||||
select -assert-count 2 t:$pmux
|
||||
design -stash gate
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
Loading…
Reference in New Issue