mirror of https://github.com/YosysHQ/yosys.git
add support for RTLIL cells with multiple outputs to the functional backend, implement $fa,$lcu,$alu
This commit is contained in:
Emily Schmidt
parent
13bacc5c8f
commit
3cd5f4ed83
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@ -18,6 +18,7 @@
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*/
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#include "kernel/functionalir.h"
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#include <optional>
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YOSYS_NAMESPACE_BEGIN
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@ -172,8 +173,38 @@ private:
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y = factory.mux(y, factory.slice(b, a.width() * i, a.width()), factory.slice(s, i, 1));
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return y;
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}
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dict<IdString, Node> handle_fa(Node a, Node b, Node c) {
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Node t1 = factory.bitwise_xor(a, b);
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Node t2 = factory.bitwise_and(a, b);
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Node t3 = factory.bitwise_and(c, t1);
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Node y = factory.bitwise_xor(c, t1);
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Node x = factory.bitwise_or(t2, t3);
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return {{ID(X), x}, {ID(Y), y}};
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}
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Node handle_lcu(Node p, Node g, Node ci) {
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Node rv = factory.bitwise_or(factory.slice(g, 0, 1), factory.bitwise_and(factory.slice(p, 0, 1), ci));
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Node c = rv;
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for(int i = 1; i < p.width(); i++) {
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c = factory.bitwise_or(factory.slice(g, i, 1), factory.bitwise_and(factory.slice(p, i, 1), c));
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rv = factory.concat(rv, c);
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}
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return rv;
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}
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dict<IdString, Node> handle_alu(Node a_in, Node b_in, int y_width, bool is_signed, Node ci, Node bi) {
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Node a = factory.extend(a_in, y_width, is_signed);
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Node b_uninverted = factory.extend(b_in, y_width, is_signed);
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Node b = factory.mux(b_uninverted, factory.bitwise_not(b_uninverted), bi);
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Node x = factory.bitwise_xor(a, b);
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Node a_extra = factory.extend(a, y_width + 1, false);
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Node b_extra = factory.extend(b, y_width + 1, false);
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Node y_extra = factory.add(factory.add(a_extra, b_extra), factory.extend(ci, a.width() + 1, false));
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Node y = factory.slice(y_extra, 0, y_width);
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Node carries = factory.bitwise_xor(y_extra, factory.bitwise_xor(a_extra, b_extra));
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Node co = factory.slice(carries, 1, y_width);
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return {{ID(X), x}, {ID(Y), y}, {ID(CO), co}};
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}
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public:
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Node handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, Node> inputs)
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std::variant<dict<IdString, Node>, Node> handle(IdString cellType, dict<IdString, Const> parameters, dict<IdString, Node> inputs)
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{
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int a_width = parameters.at(ID(A_WIDTH), Const(-1)).as_int();
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int b_width = parameters.at(ID(B_WIDTH), Const(-1)).as_int();
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@ -360,17 +391,23 @@ public:
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Node s = factory.extend(inputs.at(ID(S)), b_width, false);
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Node b = factory.mul(s, factory.constant(Const(width, b_width)));
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return factory.logical_shift_left(a, b);
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} else if(cellType == ID($fa)) {
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return handle_fa(inputs.at(ID(A)), inputs.at(ID(B)), inputs.at(ID(C)));
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} else if(cellType == ID($lcu)) {
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return handle_lcu(inputs.at(ID(P)), inputs.at(ID(G)), inputs.at(ID(CI)));
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} else if(cellType == ID($alu)) {
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return handle_alu(inputs.at(ID(A)), inputs.at(ID(B)), y_width, a_signed && b_signed, inputs.at(ID(CI)), inputs.at(ID(BI)));
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} else {
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log_error("unhandled cell in CellSimplifier %s\n", cellType.c_str());
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log_error("`%s' cells are not supported by the functional backend\n", cellType.c_str());
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}
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}
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};
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class FunctionalIRConstruction {
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using Node = FunctionalIR::Node;
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std::deque<DriveSpec> queue;
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std::deque<std::variant<DriveSpec, Cell *>> queue;
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dict<DriveSpec, Node> graph_nodes;
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idict<Cell *> cells;
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dict<std::pair<Cell *, IdString>, Node> cell_outputs;
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DriverMap driver_map;
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FunctionalIR::Factory& factory;
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CellSimplifier simplifier;
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@ -388,6 +425,24 @@ class FunctionalIRConstruction {
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}else
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return it->second;
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}
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Node enqueue_cell(Cell *cell, IdString port_name)
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{
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auto it = cell_outputs.find({cell, port_name});
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if(it == cell_outputs.end()) {
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queue.emplace_back(cell);
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std::optional<Node> rv;
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for(auto const &[name, sigspec] : cell->connections())
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if(driver_map.celltypes.cell_output(cell->type, name)) {
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auto node = factory.create_pending(sigspec.size());
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factory.suggest_name(node, cell->name.str() + "$" + name.str());
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cell_outputs.emplace({cell, name}, node);
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if(name == port_name)
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rv = node;
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}
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return *rv;
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} else
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return it->second;
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}
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public:
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FunctionalIRConstruction(FunctionalIR::Factory &f) : factory(f), simplifier(f) {}
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void add_module(Module *module)
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@ -395,7 +450,7 @@ public:
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driver_map.add(module);
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for (auto cell : module->cells()) {
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if (cell->type.in(ID($assert), ID($assume), ID($cover), ID($check)))
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enqueue(DriveBitMarker(cells(cell), 0));
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queue.emplace_back(cell);
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}
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for (auto wire : module->wires()) {
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if (wire->port_output) {
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@ -441,10 +496,44 @@ public:
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factory.declare_state_memory(node, mem->cell->name, addr_width, data_width);
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return concatenate_read_results(mem, read_results);
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}
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void process_cell(Cell *cell)
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{
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if (cell->is_mem_cell()) {
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Mem *mem = memories.at(cell, nullptr);
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log_assert(mem != nullptr);
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Node node = handle_memory(mem);
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factory.update_pending(cell_outputs.at({cell, ID(RD_DATA)}), node);
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} else {
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dict<IdString, Node> connections;
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IdString output_name; // for the single output case
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int n_outputs = 0;
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for(auto const &[name, sigspec] : cell->connections()) {
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if(driver_map.celltypes.cell_input(cell->type, name))
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connections.insert({ name, enqueue(DriveChunkPort(cell, {name, sigspec})) });
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if(driver_map.celltypes.cell_output(cell->type, name)) {
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output_name = name;
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n_outputs++;
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}
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}
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std::variant<dict<IdString, Node>, Node> outputs = simplifier.handle(cell->type, cell->parameters, connections);
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if(auto *nodep = std::get_if<Node>(&outputs); nodep != nullptr) {
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log_assert(n_outputs == 1);
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factory.update_pending(cell_outputs.at({cell, output_name}), *nodep);
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} else {
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for(auto [name, node] : std::get<dict<IdString, Node>>(outputs))
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factory.update_pending(cell_outputs.at({cell, name}), node);
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}
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}
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}
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void process_queue()
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{
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for (; !queue.empty(); queue.pop_front()) {
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DriveSpec spec = queue.front();
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if(auto p = std::get_if<Cell *>(&queue.front()); p != nullptr) {
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process_cell(*p);
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continue;
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}
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DriveSpec spec = std::get<DriveSpec>(queue.front());
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Node pending = graph_nodes.at(spec);
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if (spec.chunks().size() > 1) {
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@ -492,11 +581,7 @@ public:
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}
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else
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{
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Node cell = enqueue(DriveChunkMarker(cells(port_chunk.cell), 0, port_chunk.width));
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factory.suggest_name(cell, port_chunk.cell->name);
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//Node node = factory.cell_output(cell, port_chunk.cell->type, port_chunk.port, port_chunk.width);
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Node node = cell;
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factory.suggest_name(node, port_chunk.cell->name.str() + "$" + port_chunk.port.str());
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Node node = enqueue_cell(port_chunk.cell, port_chunk.port);
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factory.update_pending(pending, node);
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}
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} else {
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@ -518,22 +603,6 @@ public:
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args.push_back(enqueue(driver));
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Node node = factory.multiple(args, chunk.size());
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factory.update_pending(pending, node);
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} else if (chunk.is_marker()) {
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Cell *cell = cells[chunk.marker().marker];
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if (cell->is_mem_cell()) {
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Mem *mem = memories.at(cell, nullptr);
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log_assert(mem != nullptr);
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Node node = handle_memory(mem);
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factory.update_pending(pending, node);
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} else {
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dict<IdString, Node> connections;
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for(auto const &conn : cell->connections()) {
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if(driver_map.celltypes.cell_input(cell->type, conn.first))
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connections.insert({ conn.first, enqueue(DriveChunkPort(cell, conn)) });
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}
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Node node = simplifier.handle(cell->type, cell->parameters, connections);
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factory.update_pending(pending, node);
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}
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} else if (chunk.is_none()) {
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Node node = factory.undriven(chunk.size());
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factory.update_pending(pending, node);
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@ -123,6 +123,21 @@ class SliceCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['A_WIDTH', 'OFFSET', 'Y_WIDTH'], {'A': 'A_WIDTH'}, {'Y': 'Y_WIDTH'}, values)
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class FACell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['WIDTH'], {'A': 'WIDTH', 'B': 'WIDTH', 'C': 'WIDTH'}, {'X': 'WIDTH', 'Y': 'WIDTH'}, values)
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self.sim_preprocessing = "techmap" # because FA is not implemented in yosys sim
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class LCUCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['WIDTH'], {'P': 'WIDTH', 'G': 'WIDTH', 'CI': 1}, {'CO': 'WIDTH'}, values)
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self.sim_preprocessing = "techmap" # because LCU is not implemented in yosys sim
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class ALUCell(BaseCell):
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def __init__(self, name, values):
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super().__init__(name, ['A_WIDTH', 'B_WIDTH', 'Y_WIDTH', 'A_SIGNED', 'B_SIGNED'], {'A': 'A_WIDTH', 'B': 'B_WIDTH', 'CI': 1, 'BI': 1}, {'X': 'Y_WIDTH', 'Y': 'Y_WIDTH', 'CO': 'Y_WIDTH'}, values)
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self.sim_preprocessing = "techmap" # because ALU is not implemented in yosys sim
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class FailCell(BaseCell):
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def __init__(self, name):
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super().__init__(name, [], {}, {})
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@ -231,9 +246,9 @@ rtlil_cells = [
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ShiftCell("sshr", shift_widths),
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ShiftCell("shift", shift_widths),
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ShiftCell("shiftx", shift_widths),
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# ("fa", ["A", "B", "C", "X", "Y"]),
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# ("lcu", ["P", "G", "CI", "CO"]),
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# ("alu", ["A", "B", "CI", "BI", "X", "Y", "CO"]),
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FACell("fa", [8, 20]),
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LCUCell("lcu", [1, 10]),
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ALUCell("alu", binary_widths),
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BinaryCell("lt", binary_widths),
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BinaryCell("le", binary_widths),
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BinaryCell("eq", binary_widths),
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@ -27,9 +27,9 @@ def yosys_synth(verilog_file, rtlil_file):
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yosys(f"read_verilog {quote(verilog_file)} ; prep ; clk2fflogic ; write_rtlil {quote(rtlil_file)}")
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# simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file
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def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file):
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def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""):
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try:
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yosys(f"read_rtlil {quote(rtlil_file)}; sim -r {quote(vcd_reference_file)} -scope gold -vcd {quote(vcd_out_file)} -timescale 1us -sim-gold")
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yosys(f"read_rtlil {quote(rtlil_file)}; {preprocessing}; sim -r {quote(vcd_reference_file)} -scope gold -vcd {quote(vcd_out_file)} -timescale 1us -sim-gold")
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except:
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# if yosys sim fails it's probably because of a simulation mismatch
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# since yosys sim aborts on simulation mismatch to generate vcd output
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@ -53,7 +53,7 @@ def test_cxx(cell, parameters, tmp_path, num_steps, rnd):
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compile_cpp(vcdharness_cc_file, vcdharness_exe_file, ['-I', tmp_path, '-I', str(base_path / 'backends/functional/cxx_runtime')])
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seed = str(rnd(cell.name + "-cxx").getrandbits(32))
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run([str(vcdharness_exe_file.resolve()), str(vcd_functional_file), str(num_steps), str(seed)])
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yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file)
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yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
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def test_smt(cell, parameters, tmp_path, num_steps, rnd):
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import smt_vcd
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@ -67,4 +67,4 @@ def test_smt(cell, parameters, tmp_path, num_steps, rnd):
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yosys(f"read_rtlil {quote(rtlil_file)} ; write_functional_smt2 {quote(smt_file)}")
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run(['z3', smt_file]) # check if output is valid smtlib before continuing
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smt_vcd.simulate_smt(smt_file, vcd_functional_file, num_steps, rnd(cell.name + "-smt"))
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yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file)
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yosys_sim(rtlil_file, vcd_functional_file, vcd_yosys_sim_file, getattr(cell, 'sim_preprocessing', ''))
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