rtlil: Add `Design::select()` for selecting whole modules.

This commit is contained in:
Alberto Gonzalez 2020-06-17 20:28:56 +00:00
parent d5d0cc88d2
commit 3ccdab940c
No known key found for this signature in database
GPG Key ID: 8395A8BA109708B2
1 changed files with 7 additions and 0 deletions

View File

@ -1061,6 +1061,13 @@ struct RTLIL::Design
return selected_member(module->name, member->name);
}
template<typename T1> void select(T1 *module) {
if (selection_stack.size() > 0) {
RTLIL::Selection &sel = selection_stack.back();
sel.select(module);
}
}
template<typename T1, typename T2> void select(T1 *module, T2 *member) {
if (selection_stack.size() > 0) {
RTLIL::Selection &sel = selection_stack.back();