mirror of https://github.com/YosysHQ/yosys.git
Wider range of cell types supported in "share" pass
This commit is contained in:
Clifford Wolf
parent
c54d1f2ad1
commit
3cb61d03f8
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@ -30,11 +30,14 @@ struct ShareWorkerConfig
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bool opt_force;
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bool opt_aggressive;
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bool opt_fast;
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std::set<std::string> generic_uni_ops, generic_bin_ops, generic_cbin_ops;
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};
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struct ShareWorker
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{
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ShareWorkerConfig config;
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std::set<std::string> generic_ops;
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RTLIL::Design *design;
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RTLIL::Module *module;
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@ -125,19 +128,19 @@ struct ShareWorker
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}
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if (cell->type == "$mul" || cell->type == "$div" || cell->type == "$mod") {
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if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 4)
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if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 4)
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shareable_cells.insert(cell);
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continue;
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}
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if (cell->type == "$shl" || cell->type == "$shr" || cell->type == "$sshl" || cell->type == "$sshr") {
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if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 8)
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if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 8)
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shareable_cells.insert(cell);
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continue;
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}
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if (cell->type == "$add" || cell->type == "$sub") {
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if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() > 10)
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if (generic_ops.count(cell->type)) {
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if (config.opt_aggressive || cell->parameters.at("\\Y_WIDTH").as_int() >= 10)
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shareable_cells.insert(cell);
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continue;
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}
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@ -157,15 +160,25 @@ struct ShareWorker
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return true;
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}
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if (c1->type == "$mul" || c1->type == "$div" || c1->type == "$mod" || c1->type == "$add" || c1->type == "$sub" ||
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c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr")
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if (config.generic_uni_ops.count(c1->type))
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{
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if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
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return false;
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if (!config.opt_aggressive)
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{
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int a1_width = c1->parameters.at("\\A_WIDTH").as_int();
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int y1_width = c1->parameters.at("\\Y_WIDTH").as_int();
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if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool())
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return false;
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int a2_width = c2->parameters.at("\\A_WIDTH").as_int();
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int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
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if (std::max(a1_width, a2_width) > 2 * std::min(a1_width, a2_width)) return false;
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if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false;
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}
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return true;
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}
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if (config.generic_bin_ops.count(c1->type))
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{
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if (!config.opt_aggressive)
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{
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int a1_width = c1->parameters.at("\\A_WIDTH").as_int();
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@ -184,6 +197,32 @@ struct ShareWorker
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return true;
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}
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if (config.generic_cbin_ops.count(c1->type))
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{
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if (!config.opt_aggressive)
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{
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int a1_width = c1->parameters.at("\\A_WIDTH").as_int();
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int b1_width = c1->parameters.at("\\B_WIDTH").as_int();
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int y1_width = c1->parameters.at("\\Y_WIDTH").as_int();
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int a2_width = c2->parameters.at("\\A_WIDTH").as_int();
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int b2_width = c2->parameters.at("\\B_WIDTH").as_int();
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int y2_width = c2->parameters.at("\\Y_WIDTH").as_int();
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int min1_width = std::min(a1_width, b1_width);
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int max1_width = std::max(a1_width, b1_width);
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int min2_width = std::min(a2_width, b2_width);
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int max2_width = std::max(a2_width, b2_width);
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if (std::max(min1_width, min2_width) > 2 * std::min(min1_width, min2_width)) return false;
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if (std::max(max1_width, max2_width) > 2 * std::min(max1_width, max2_width)) return false;
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if (std::max(y1_width, y2_width) > 2 * std::min(y1_width, y2_width)) return false;
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}
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return true;
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}
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for (auto &it : c1->parameters)
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if (c2->parameters.count(it.first) == 0 || c2->parameters.at(it.first) != it.second)
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return false;
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@ -210,10 +249,106 @@ struct ShareWorker
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RTLIL::Cell *make_supercell(RTLIL::Cell *c1, RTLIL::Cell *c2, RTLIL::SigSpec act)
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{
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if (c1->type == "$mul" || c1->type == "$div" || c1->type == "$mod" || c1->type == "$add" || c1->type == "$sub" ||
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c1->type == "$shl" || c1->type == "$shr" || c1->type == "$sshl" || c1->type == "$sshr")
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log_assert(c1->type == c2->type);
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if (config.generic_uni_ops.count(c1->type))
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{
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log_assert(c1->type == c2->type);
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if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
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{
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RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
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if (unsigned_cell->connections.at("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
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unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
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unsigned_cell->connections.at("\\A").append_bit(RTLIL::State::S0);
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}
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unsigned_cell->parameters.at("\\A_SIGNED") = true;
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unsigned_cell->check();
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}
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bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool();
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log_assert(a_signed == c2->parameters.at("\\A_SIGNED").as_bool());
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RTLIL::SigSpec a1 = c1->connections.at("\\A");
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RTLIL::SigSpec y1 = c1->connections.at("\\Y");
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RTLIL::SigSpec a2 = c2->connections.at("\\A");
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RTLIL::SigSpec y2 = c2->connections.at("\\Y");
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int a_width = std::max(a1.width, a2.width);
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int y_width = std::max(y1.width, y2.width);
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if (a1.width != a_width) a1 = module->addPos(NEW_ID, a1, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y");
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if (a2.width != a_width) a2 = module->addPos(NEW_ID, a2, module->new_wire(a_width, NEW_ID), a_signed)->connections.at("\\Y");
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RTLIL::SigSpec a = module->Mux(NEW_ID, a2, a1, act);
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RTLIL::Wire *y = module->new_wire(y_width, NEW_ID);
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RTLIL::Cell *supercell = new RTLIL::Cell;
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supercell->name = NEW_ID;
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supercell->type = c1->type;
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supercell->parameters["\\A_SIGNED"] = a_signed;
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supercell->parameters["\\A_WIDTH"] = a_width;
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supercell->parameters["\\Y_WIDTH"] = y_width;
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supercell->connections["\\A"] = a;
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supercell->connections["\\Y"] = y;
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module->add(supercell);
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RTLIL::SigSpec new_y1(y, y1.width);
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RTLIL::SigSpec new_y2(y, y2.width);
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module->connections.push_back(RTLIL::SigSig(y1, new_y1));
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module->connections.push_back(RTLIL::SigSig(y2, new_y2));
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return supercell;
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}
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if (config.generic_bin_ops.count(c1->type) || config.generic_cbin_ops.count(c1->type))
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{
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bool modified_src_cells = false;
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if (config.generic_cbin_ops.count(c1->type))
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{
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int score_unflipped = std::max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int()) +
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std::max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int());
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int score_flipped = std::max(c1->parameters.at("\\A_WIDTH").as_int(), c2->parameters.at("\\B_WIDTH").as_int()) +
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std::max(c1->parameters.at("\\B_WIDTH").as_int(), c2->parameters.at("\\A_WIDTH").as_int());
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if (score_flipped < score_unflipped)
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{
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std::swap(c2->connections.at("\\A"), c2->connections.at("\\B"));
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std::swap(c2->parameters.at("\\A_WIDTH"), c2->parameters.at("\\B_WIDTH"));
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std::swap(c2->parameters.at("\\A_SIGNED"), c2->parameters.at("\\B_SIGNED"));
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modified_src_cells = true;
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}
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}
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if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool())
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{
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RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1;
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if (unsigned_cell->connections.at("\\A").to_sigbit_vector().back() != RTLIL::State::S0) {
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unsigned_cell->parameters.at("\\A_WIDTH") = unsigned_cell->parameters.at("\\A_WIDTH").as_int() + 1;
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unsigned_cell->connections.at("\\A").append_bit(RTLIL::State::S0);
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}
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unsigned_cell->parameters.at("\\A_SIGNED") = true;
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modified_src_cells = true;
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}
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if (c1->parameters.at("\\B_SIGNED").as_bool() != c2->parameters.at("\\B_SIGNED").as_bool())
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{
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RTLIL::Cell *unsigned_cell = c1->parameters.at("\\B_SIGNED").as_bool() ? c2 : c1;
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if (unsigned_cell->connections.at("\\B").to_sigbit_vector().back() != RTLIL::State::S0) {
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unsigned_cell->parameters.at("\\B_WIDTH") = unsigned_cell->parameters.at("\\B_WIDTH").as_int() + 1;
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unsigned_cell->connections.at("\\B").append_bit(RTLIL::State::S0);
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}
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unsigned_cell->parameters.at("\\B_SIGNED") = true;
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modified_src_cells = true;
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}
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if (modified_src_cells) {
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c1->check();
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c2->check();
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}
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bool a_signed = c1->parameters.at("\\A_SIGNED").as_bool();
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bool b_signed = c1->parameters.at("\\B_SIGNED").as_bool();
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@ -259,9 +394,7 @@ struct ShareWorker
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RTLIL::SigSpec b = module->Mux(NEW_ID, b2, b1, act);
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RTLIL::Wire *y = module->new_wire(y_width, NEW_ID);
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RTLIL::Cell *supercell = new RTLIL::Cell;
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supercell->name = NEW_ID;
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supercell->type = c1->type;
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RTLIL::Cell *supercell = module->addCell(NEW_ID, c1->type);
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supercell->parameters["\\A_SIGNED"] = a_signed;
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supercell->parameters["\\B_SIGNED"] = b_signed;
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supercell->parameters["\\A_WIDTH"] = a_width;
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@ -270,7 +403,7 @@ struct ShareWorker
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supercell->connections["\\A"] = a;
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supercell->connections["\\B"] = b;
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supercell->connections["\\Y"] = y;
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module->add(supercell);
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supercell->check();
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RTLIL::SigSpec new_y1(y, y1.width);
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RTLIL::SigSpec new_y2(y, y2.width);
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@ -502,6 +635,10 @@ struct ShareWorker
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ShareWorker(ShareWorkerConfig config, RTLIL::Design *design, RTLIL::Module *module) :
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config(config), design(design), module(module)
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{
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generic_ops.insert(config.generic_uni_ops.begin(), config.generic_uni_ops.end());
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generic_ops.insert(config.generic_bin_ops.begin(), config.generic_bin_ops.end());
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generic_ops.insert(config.generic_cbin_ops.begin(), config.generic_cbin_ops.end());
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fwd_ct.setup_internals();
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cone_ct.setup_internals();
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@ -752,10 +889,53 @@ struct SharePass : public Pass {
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virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
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{
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ShareWorkerConfig config;
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config.opt_force = false;
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config.opt_aggressive = false;
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config.opt_fast = false;
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config.generic_uni_ops.insert("$not");
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// config.generic_uni_ops.insert("$pos");
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// config.generic_uni_ops.insert("$bu0");
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config.generic_uni_ops.insert("$neg");
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config.generic_uni_ops.insert("$reduce_and");
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config.generic_uni_ops.insert("$reduce_or");
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config.generic_uni_ops.insert("$reduce_xor");
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config.generic_uni_ops.insert("$reduce_xnor");
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config.generic_uni_ops.insert("$reduce_bool");
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config.generic_cbin_ops.insert("$and");
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config.generic_cbin_ops.insert("$or");
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config.generic_cbin_ops.insert("$xor");
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config.generic_cbin_ops.insert("$xnor");
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config.generic_bin_ops.insert("$shl");
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config.generic_bin_ops.insert("$shr");
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config.generic_bin_ops.insert("$sshl");
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config.generic_bin_ops.insert("$sshr");
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config.generic_bin_ops.insert("$lt");
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config.generic_bin_ops.insert("$le");
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config.generic_bin_ops.insert("$eq");
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config.generic_bin_ops.insert("$ne");
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config.generic_bin_ops.insert("$eqx");
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config.generic_bin_ops.insert("$nex");
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config.generic_bin_ops.insert("$ge");
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config.generic_bin_ops.insert("$gt");
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config.generic_cbin_ops.insert("$add");
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config.generic_cbin_ops.insert("$mul");
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config.generic_bin_ops.insert("$sub");
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config.generic_bin_ops.insert("$div");
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config.generic_bin_ops.insert("$mod");
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// config.generic_bin_ops.insert("$pow");
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config.generic_uni_ops.insert("$logic_not");
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config.generic_cbin_ops.insert("$logic_and");
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config.generic_cbin_ops.insert("$logic_or");
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log_header("Executing SHARE pass (SAT-based resource sharing).\n");
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size_t argidx;
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@ -15,36 +15,58 @@ def redirect_stdout(new_target):
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finally:
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sys.stdout = old_target
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def maybe_plus_e(expr):
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def random_plus_x():
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return "%s x" % random.choice(['+', '+', '+', '-', '-', '|', '&', '^'])
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def maybe_plus_x(expr):
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if random.randint(0, 4) == 0:
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return "(%s + e)" % expr
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return "(%s %s)" % (expr, random_plus_x())
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else:
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return expr
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for idx in range(100):
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with file('temp/uut_%05d.v' % idx, 'w') as f, redirect_stdout(f):
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print('module uut_%05d(a, b, c, d, e, s, y);' % (idx))
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ac_signed = random.choice(['', ' signed'])
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bd_signed = random.choice(['', ' signed'])
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op = random.choice(['+', '-', '*', '/', '%', '<<', '>>', '<<<', '>>>'])
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print(' input%s [%d:0] a;' % (ac_signed, random.randint(0, 8)))
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print(' input%s [%d:0] b;' % (bd_signed, random.randint(0, 8)))
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print(' input%s [%d:0] c;' % (ac_signed, random.randint(0, 8)))
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print(' input%s [%d:0] d;' % (bd_signed, random.randint(0, 8)))
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print(' input signed [%d:0] e;' % random.randint(0, 8))
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print(' input s;')
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print(' output [%d:0] y;' % random.randint(0, 8))
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print(' assign y = (s ? %s(%s %s %s) : %s(%s %s %s))%s;' %
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(random.choice(['', '$signed', '$unsigned']), maybe_plus_e('a'), op, maybe_plus_e('b'),
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random.choice(['', '$signed', '$unsigned']), maybe_plus_e('c'), op, maybe_plus_e('d'),
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' + e' if random.randint(0, 4) == 0 else ''))
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print('endmodule')
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if random.choice(['bin', 'uni']) == 'bin':
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print('module uut_%05d(a, b, c, d, x, s, y);' % (idx))
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op = random.choice([
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random.choice(['+', '-', '*', '/', '%']),
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random.choice(['<', '<=', '==', '!=', '===', '!==', '>=', '>' ]),
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random.choice(['<<', '>>', '<<<', '>>>']),
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random.choice(['|', '&', '^', '~^', '||', '&&']),
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])
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print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input%s [%d:0] c;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input%s [%d:0] d;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input s;')
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print(' output [%d:0] y;' % random.randint(0, 8))
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print(' assign y = (s ? %s(%s %s %s) : %s(%s %s %s))%s;' %
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(random.choice(['', '$signed', '$unsigned']), maybe_plus_x('a'), op, maybe_plus_x('b'),
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random.choice(['', '$signed', '$unsigned']), maybe_plus_x('c'), op, maybe_plus_x('d'),
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random_plus_x() if random.randint(0, 4) == 0 else ''))
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print('endmodule')
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else:
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print('module uut_%05d(a, b, x, s, y);' % (idx))
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op = random.choice(['~', '-', '!'])
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print(' input%s [%d:0] a;' % (random.choice(['', ' signed']), random.randint(0, 8)))
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print(' input%s [%d:0] b;' % (random.choice(['', ' signed']), random.randint(0, 8)))
|
||||
print(' input%s [%d:0] x;' % (random.choice(['', ' signed']), random.randint(0, 8)))
|
||||
print(' input s;')
|
||||
print(' output [%d:0] y;' % random.randint(0, 8))
|
||||
print(' assign y = (s ? %s(%s%s) : %s(%s%s))%s;' %
|
||||
(random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('a'),
|
||||
random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('b'),
|
||||
random_plus_x() if random.randint(0, 4) == 0 else ''))
|
||||
print('endmodule')
|
||||
with file('temp/uut_%05d.ys' % idx, 'w') as f, redirect_stdout(f):
|
||||
print('read_verilog temp/uut_%05d.v' % idx)
|
||||
print('proc;;')
|
||||
print('copy uut_%05d gold' % idx)
|
||||
print('rename uut_%05d gate' % idx)
|
||||
print('share -aggressive gate')
|
||||
print('tee -a temp/all_share_log.txt log')
|
||||
print('tee -a temp/all_share_log.txt log #job# uut_%05d' % idx)
|
||||
print('tee -a temp/all_share_log.txt share -aggressive gate')
|
||||
print('miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter')
|
||||
print('sat -set-def-inputs -verify -prove trigger 0 -show-inputs -show-outputs miter')
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,8 @@
|
|||
#!/bin/bash
|
||||
|
||||
# run this test many times:
|
||||
# time bash -c 'for ((i=0; i<100; i++)); do echo "-- $i --"; bash run-test.sh || exit 1; done'
|
||||
|
||||
set -e
|
||||
|
||||
rm -rf temp
|
||||
|
|
@ -14,3 +18,10 @@ for i in $( ls temp/*.ys | sed 's,[^0-9],,g; s,^0*\(.\),\1,g;' ); do
|
|||
done
|
||||
echo
|
||||
|
||||
failed_share=$( echo $( gawk '/^#job#/ { j=$2; db[j]=0; } /^Removing [24] cells/ { delete db[j]; } END { for (j in db) print(j); }' temp/all_share_log.txt ) )
|
||||
if [ -n "$failed_share" ]; then
|
||||
echo "Resource sharing failed for the following test cases: $failed_share"
|
||||
false
|
||||
fi
|
||||
|
||||
exit 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue