From 3c5b0ab1641409a09252b488c7f08ced631753d8 Mon Sep 17 00:00:00 2001
From: "N. Engelhardt" <nak@yosyshq.com>
Date: Fri, 1 Dec 2023 10:47:39 +0100
Subject: [PATCH] fix test setup for synth_quicklogic memory tests

---
 tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys  |  5 +-
 .../arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v  |  2 +-
 .../quicklogic/qlf_k6n10f/gen_memories.py     | 47 +++++++------------
 tests/arch/quicklogic/qlf_k6n10f/mem_tb.v     |  2 +-
 tests/arch/quicklogic/qlf_k6n10f/run-test.sh  |  1 +
 5 files changed, 21 insertions(+), 36 deletions(-)

diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys
index 635769cc0..ccce5882f 100644
--- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys
+++ b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp.ys
@@ -1,8 +1,7 @@
 read_verilog bram_tdp.v
 hierarchy -top BRAM_TDP
 synth_quicklogic -family qlf_k6n10f
-read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
 read_verilog -formal bram_tdp_tb.v
-hierarchy -top TB
-proc
+read_verilog -overwrite +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
+prep -top TB
 sim -clock clk -n 20 -assert # -vcd bram_tdp.vcd
diff --git a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v
index 5d4fbe067..351c334d0 100644
--- a/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v
+++ b/tests/arch/quicklogic/qlf_k6n10f/bram_tdp_tb.v
@@ -57,7 +57,7 @@ wire [DATA_WIDTH-1:0] wd_a = wd_a_testvector[i];
 
 wire rce_b = rce_b_testvector[i];
 wire [ADDR_WIDTH-1:0] ra_b = ra_b_testvector[i];
-wire [DATA_WIDTH-1:0] rq_b = rq_b_expected[i];
+wire [DATA_WIDTH-1:0] rq_b;
 
 wire wce_b = wce_b_testvector[i];
 wire [ADDR_WIDTH-1:0] wa_b = wa_b_testvector[i];
diff --git a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py
index 631289800..1d596b3c7 100644
--- a/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py
+++ b/tests/arch/quicklogic/qlf_k6n10f/gen_memories.py
@@ -4,11 +4,11 @@ from dataclasses import dataclass
 
 
 blockram_template = """# ======================================
+log ** GENERATING TEST {top} WITH PARAMS{param_str}
 design -reset; read_verilog -defer ../../common/blockram.v
 chparam{param_str} {top}
 hierarchy -top {top}
-synth_quicklogic -family qlf_k6n10f -top {top}; cd {top}
-log ** TESTING {top} WITH PARAMS{param_str}\
+synth_quicklogic -family qlf_k6n10f -top {top}
 """
 blockram_tests: "list[tuple[list[tuple[str, int]], str, list[str]]]" = [
     # TDP36K = 1024x36bit RAM, 2048x18bit or 4096x9bit also work
@@ -103,8 +103,10 @@ blockram_tests: "list[tuple[list[tuple[str, int]], str, list[str]]]" = [
 ]
 
 sim_template = """\
-cd
-read_verilog +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
+design -stash synthesized
+design -copy-from synthesized -as {top}_synth {top}
+design -delete synthesized
+read_verilog +/quicklogic/common/cells_sim.v +/quicklogic/qlf_k6n10f/cells_sim.v +/quicklogic/qlf_k6n10f/brams_sim.v +/quicklogic/qlf_k6n10f/sram1024x18_mem.v +/quicklogic/qlf_k6n10f/ufifo_ctl.v +/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
 read_verilog <<EOF
 `define MEM_TEST_VECTOR {mem_test_vector}
 
@@ -113,17 +115,14 @@ read_verilog <<EOF
 EOF
 read_verilog -defer -formal mem_tb.v
 chparam{param_str} -set VECTORLEN {vectorlen} TB
-read_verilog +/quicklogic/qlf_k6n10f/cells_sim.v
 hierarchy -top TB -check
-proc
+prep
+log ** CHECKING SIMULATION FOR TEST {top} WITH PARAMS{param_str}
 sim -clock clk -n {vectorlen} -assert
 """
 
 sync_ram_sdp_submodule = """\
-sync_ram_sdp #(\\
-	.ADDRESS_WIDTH(ADDRESS_WIDTH),\\
-	.DATA_WIDTH(DATA_WIDTH)\\
-) uut (\\
+sync_ram_sdp_synth uut (\\
 	.clk(clk),\\
 	.address_in_r(ra_a),\\
 	.data_out(rq_a),\\
@@ -134,10 +133,7 @@ sync_ram_sdp #(\\
 """
 
 sync_ram_tdp_submodule = """\
-sync_ram_tdp #(\\
-	.ADDRESS_WIDTH(ADDRESS_WIDTH),\\
-	.DATA_WIDTH(DATA_WIDTH)\\
-) uut (\\
+sync_ram_tdp_synth uut (\\
 	.clk_a(clk),\\
 	.clk_b(clk),\\
 	.write_enable_a(wce_a),\\
@@ -154,11 +150,7 @@ sync_ram_tdp #(\\
 """
 
 sync_ram_sdp_wwr_submodule = """\
-sync_ram_sdp_wwr #(\\
-	.ADDRESS_WIDTH(ADDRESS_WIDTH),\\
-	.DATA_WIDTH(DATA_WIDTH),\\
-	.SHIFT_VAL(SHIFT_VAL)\\
-) uut (\\
+sync_ram_sdp_wwr_synth uut (\\
 	.clk_w(clk),\\
 	.clk_r(clk),\\
 	.write_enable(wce_a),\\
@@ -170,11 +162,7 @@ sync_ram_sdp_wwr #(\\
 """
 
 sync_ram_sdp_wrr_submodule = """\
-sync_ram_sdp_wrr #(\\
-	.ADDRESS_WIDTH(ADDRESS_WIDTH),\\
-	.DATA_WIDTH(DATA_WIDTH),\\
-	.SHIFT_VAL(SHIFT_VAL)\\
-) uut (\\
+sync_ram_sdp_wrr_synth uut (\\
 	.clk_w(clk),\\
 	.clk_r(clk),\\
 	.write_enable(wce_a),\\
@@ -186,18 +174,13 @@ sync_ram_sdp_wrr #(\\
 """
 
 double_sync_ram_sdp_submodule = """\
-double_sync_ram_sdp #(\\
-	.ADDRESS_WIDTH_A(ADDRESS_WIDTH_A),\\
-	.DATA_WIDTH_A(DATA_WIDTH_A),\\
-	.ADDRESS_WIDTH_B(ADDRESS_WIDTH_B),\\
-	.DATA_WIDTH_B(DATA_WIDTH_B)\\
-) uut (\\
+double_sync_ram_sdp_synth uut (\\
 	.clk_a(clk),\\
 	.write_enable_a(wce_a),\\
 	.address_in_w_a(wa_a),\\
 	.address_in_r_a(ra_a),\\
 	.data_in_a(wd_a),\\
-	.data_out_b(rq_b),\\
+	.data_out_a(rq_a),\\
 	.clk_b(clk),\\
 	.write_enable_b(wce_b),\\
 	.address_in_w_b(wa_b),\\
@@ -419,6 +402,7 @@ for sim_test in sim_tests:
             file=f
         )
         for assertion in sim_test.assertions:
+            print("log ** CHECKING CELL COUNTS FOR TEST {top} WITH PARAMS{param_str}".format(param_str=param_str, top=top), file=f)
             print("select {}".format(assertion), file=f)
         print("", file=f)
 
@@ -444,6 +428,7 @@ for sim_test in sim_tests:
                     mem_test_vector += f"\\\n{key}[{step}] = 'h{val:x};"
             print(
                 sim_template.format(
+                    top=top,
                     mem_test_vector=mem_test_vector,
                     uut_submodule=uut_submodule,
                     param_str=param_str,
diff --git a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
index cb64269a1..89e41f8bc 100644
--- a/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
+++ b/tests/arch/quicklogic/qlf_k6n10f/mem_tb.v
@@ -8,7 +8,7 @@ parameter DATA_WIDTH_A = DATA_WIDTH;
 parameter DATA_WIDTH_B = DATA_WIDTH;
 parameter VECTORLEN = 16;
 parameter SHIFT_VAL = 0;
-localparam MAX_WIDTH = 36;
+localparam MAX_WIDTH = DATA_WIDTH;
 
 reg rce_a_testvector [VECTORLEN-1:0];
 reg [ADDRESS_WIDTH_A-1:0] ra_a_testvector [VECTORLEN-1:0];
diff --git a/tests/arch/quicklogic/qlf_k6n10f/run-test.sh b/tests/arch/quicklogic/qlf_k6n10f/run-test.sh
index 36689edde..be16b7829 100755
--- a/tests/arch/quicklogic/qlf_k6n10f/run-test.sh
+++ b/tests/arch/quicklogic/qlf_k6n10f/run-test.sh
@@ -1,4 +1,5 @@
 #!/usr/bin/env bash
 set -eu
+python3 gen_memories.py
 source ../../../gen-tests-makefile.sh
 run_tests --yosys-scripts --bash