mirror of https://github.com/YosysHQ/yosys.git
rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)
Converting to a pool<SigBit> is fairly expensive due to inserts somewhat frequently causing rehashing. Instead, walk through the pattern SigSpec directly on a chunk-by-chunk basis and apply it to this SigSpec's individual bits. Using chunks for the pattern minimizes the number of iterations in the outer loop.
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@ -2777,8 +2777,37 @@ void RTLIL::SigSpec::remove2(const std::set<RTLIL::SigBit> &pattern, RTLIL::SigS
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RTLIL::SigSpec RTLIL::SigSpec::extract(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec *other) const
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{
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pool<RTLIL::SigBit> pattern_bits = pattern.to_sigbit_pool();
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return extract(pattern_bits, other);
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if (other)
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cover("kernel.rtlil.sigspec.extract_other");
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else
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cover("kernel.rtlil.sigspec.extract");
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log_assert(other == NULL || width_ == other->width_);
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RTLIL::SigSpec ret;
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std::vector<RTLIL::SigBit> bits_match = to_sigbit_vector();
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for (auto& pattern_chunk : pattern.chunks()) {
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if (other) {
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std::vector<RTLIL::SigBit> bits_other = other->to_sigbit_vector();
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for (int i = 0; i < width_; i++)
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if (bits_match[i].wire &&
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bits_match[i].wire == pattern_chunk.wire &&
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bits_match[i].offset >= pattern_chunk.offset &&
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bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
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ret.append_bit(bits_other[i]);
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} else {
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for (int i = 0; i < width_; i++)
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if (bits_match[i].wire &&
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bits_match[i].wire == pattern_chunk.wire &&
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bits_match[i].offset >= pattern_chunk.offset &&
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bits_match[i].offset < pattern_chunk.offset + pattern_chunk.width)
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ret.append_bit(bits_match[i]);
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}
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}
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ret.check();
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return ret;
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}
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RTLIL::SigSpec RTLIL::SigSpec::extract(const pool<RTLIL::SigBit> &pattern, const RTLIL::SigSpec *other) const
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