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Merge pull request #1338 from YosysHQ/eddie/deferred_top
hierarchy -auto-top to work with (* top *) modules from read/read_verilog -defer
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3c462e5eeb
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@ -1099,6 +1099,13 @@ static AstModule* process_module(AstNode *ast, bool defer, AstNode *original_ast
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ignoreThisSignalsInInitial = RTLIL::SigSpec();
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}
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else {
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for (auto &attr : ast->attributes) {
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if (attr.second->type != AST_CONSTANT)
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continue;
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current_module->attributes[attr.first] = attr.second->asAttrConst();
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}
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}
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if (ast->type == AST_INTERFACE)
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current_module->set_bool_attribute("\\is_interface");
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@ -808,6 +808,30 @@ struct HierarchyPass : public Pass {
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if (mod_it.second->get_bool_attribute("\\top"))
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top_mod = mod_it.second;
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if (top_mod != nullptr && top_mod->name.begins_with("$abstract")) {
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IdString top_name = top_mod->name.substr(strlen("$abstract"));
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dict<RTLIL::IdString, RTLIL::Const> top_parameters;
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for (auto ¶ : parameters) {
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SigSpec sig_value;
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if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second))
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log_cmd_error("Can't decode value '%s'!\n", para.second.c_str());
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top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const();
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}
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top_mod = design->module(top_mod->derive(design, top_parameters));
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if (top_mod != nullptr && top_mod->name != top_name) {
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Module *m = top_mod->clone();
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m->name = top_name;
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Module *old_mod = design->module(top_name);
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if (old_mod)
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design->remove(old_mod);
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design->add(m);
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top_mod = m;
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}
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}
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if (top_mod == nullptr && auto_top_mode) {
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log_header(design, "Finding top of design hierarchy..\n");
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dict<Module*, int> db;
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@ -0,0 +1,27 @@
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read -noverific
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read -vlog2k <<EOT
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module first;
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endmodule
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(* top *)
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module top(input i, output o);
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sub s0(i, o);
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endmodule
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(* constant_expression=1+1?2*2:3/3 *)
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module sub(input i, output o);
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assign o = ~i;
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endmodule
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EOT
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design -save read
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hierarchy -auto-top
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select -assert-any top
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select -assert-any sub
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select -assert-none foo
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design -load read
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hierarchy
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select -assert-any top
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select -assert-any sub
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select -assert-none foo
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