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Fix ordering of when to insert zero index

This commit is contained in:
Eddie Hung 2019-04-11 16:25:59 -07:00
parent f587950bde
commit 3c1f1a6605
1 changed files with 1 additions and 2 deletions
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3
passes/techmap/pmux2shiftx.cc
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@ -65,8 +65,7 @@ struct Pmux2ShiftxPass : public Pass {
const int clog2width = ceil(log2(s_width));
RTLIL::SigSpec pmux_b;
pmux_b.append(RTLIL::Const(0, clog2width));
for (int i = s_width-1; i > 0; i--)
for (int i = s_width-1; i >= 0; i--)
pmux_b.append(RTLIL::Const(i, clog2width));
shiftx_a.append(cell->getPort("\\B"));
pmux_s.append(cell->getPort("\\S"));