mirror of https://github.com/YosysHQ/yosys.git
Fix equiv_simple, old behavior now available with "equiv_simple -short"
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@ -35,13 +35,14 @@ struct EquivSimpleWorker
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ezSatPtr ez;
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SatGen satgen;
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int max_seq;
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bool short_cones;
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bool verbose;
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pool<pair<Cell*, int>> imported_cells_cache;
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EquivSimpleWorker(const vector<Cell*> &equiv_cells, SigMap &sigmap, dict<SigBit, Cell*> &bit2driver, int max_seq, bool verbose, bool model_undef) :
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EquivSimpleWorker(const vector<Cell*> &equiv_cells, SigMap &sigmap, dict<SigBit, Cell*> &bit2driver, int max_seq, bool short_cones, bool verbose, bool model_undef) :
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module(equiv_cells.front()->module), equiv_cells(equiv_cells), equiv_cell(nullptr),
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sigmap(sigmap), bit2driver(bit2driver), satgen(ez.get(), &sigmap), max_seq(max_seq), verbose(verbose)
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sigmap(sigmap), bit2driver(bit2driver), satgen(ez.get(), &sigmap), max_seq(max_seq), short_cones(short_cones), verbose(verbose)
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{
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satgen.model_undef = model_undef;
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}
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@ -142,22 +143,44 @@ struct EquivSimpleWorker
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pool<SigBit> short_bits_cone_a, short_bits_cone_b;
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pool<SigBit> input_bits;
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for (auto bit_a : seed_a)
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find_input_cone(next_seed_a, short_cells_cone_a, short_bits_cone_a, full_cells_cone_b, full_bits_cone_b, &input_bits, bit_a);
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next_seed_a.swap(seed_a);
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if (short_cones)
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{
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for (auto bit_a : seed_a)
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find_input_cone(next_seed_a, short_cells_cone_a, short_bits_cone_a, full_cells_cone_b, full_bits_cone_b, &input_bits, bit_a);
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next_seed_a.swap(seed_a);
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for (auto bit_b : seed_b)
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find_input_cone(next_seed_b, short_cells_cone_b, short_bits_cone_b, full_cells_cone_a, full_bits_cone_a, &input_bits, bit_b);
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next_seed_b.swap(seed_b);
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for (auto bit_b : seed_b)
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find_input_cone(next_seed_b, short_cells_cone_b, short_bits_cone_b, full_cells_cone_a, full_bits_cone_a, &input_bits, bit_b);
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next_seed_b.swap(seed_b);
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}
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else
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{
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short_cells_cone_a = full_cells_cone_a;
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short_bits_cone_a = full_bits_cone_a;
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next_seed_a.swap(seed_a);
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short_cells_cone_b = full_cells_cone_b;
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short_bits_cone_b = full_bits_cone_b;
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next_seed_b.swap(seed_b);
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}
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pool<Cell*> problem_cells;
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problem_cells.insert(short_cells_cone_a.begin(), short_cells_cone_a.end());
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problem_cells.insert(short_cells_cone_b.begin(), short_cells_cone_b.end());
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if (verbose)
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{
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log(" Adding %d new cells to the problem (%d A, %d B, %d shared).\n",
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GetSize(problem_cells), GetSize(short_cells_cone_a), GetSize(short_cells_cone_b),
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(GetSize(short_cells_cone_a) + GetSize(short_cells_cone_b)) - GetSize(problem_cells));
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#if 0
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for (auto cell : short_cells_cone_a)
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log(" A-side cell: %s\n", log_id(cell));
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for (auto cell : short_cells_cone_b)
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log(" B-side cell: %s\n", log_id(cell));
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#endif
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}
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for (auto cell : problem_cells) {
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auto key = pair<Cell*, int>(cell, step+1);
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@ -264,6 +287,10 @@ struct EquivSimplePass : public Pass {
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log(" -undef\n");
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log(" enable modelling of undef states\n");
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log("\n");
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log(" -short\n");
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log(" create shorter input cones that stop at shared nodes. This yields\n");
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log(" simpler SAT problems but sometimes fails to prove equivalence.\n");
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log("\n");
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log(" -nogroup\n");
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log(" disabling grouping of $equiv cells by output wire\n");
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log("\n");
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@ -273,7 +300,7 @@ struct EquivSimplePass : public Pass {
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}
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virtual void execute(std::vector<std::string> args, Design *design)
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{
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bool verbose = false, model_undef = false, nogroup = false;
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bool verbose = false, short_cones = false, model_undef = false, nogroup = false;
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int success_counter = 0;
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int max_seq = 1;
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@ -285,6 +312,10 @@ struct EquivSimplePass : public Pass {
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verbose = true;
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continue;
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}
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if (args[argidx] == "-short") {
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short_cones = true;
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continue;
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}
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if (args[argidx] == "-undef") {
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model_undef = true;
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continue;
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@ -346,7 +377,7 @@ struct EquivSimplePass : public Pass {
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for (auto it2 : it.second)
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cells.push_back(it2.second);
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EquivSimpleWorker worker(cells, sigmap, bit2driver, max_seq, verbose, model_undef);
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EquivSimpleWorker worker(cells, sigmap, bit2driver, max_seq, short_cones, verbose, model_undef);
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success_counter += worker.run();
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}
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}
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