mirror of https://github.com/YosysHQ/yosys.git
Improve Verific importer blackbox handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -118,6 +118,18 @@ RTLIL::SigBit VerificImporter::net_map_at(Net *net)
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return net_map.at(net);
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}
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bool is_blackbox(Netlist *nl)
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{
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if (nl->IsBlackBox())
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return true;
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const char *attr = nl->GetAttValue("blackbox");
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if (attr != nullptr && strcmp(attr, "0"))
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return true;
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return false;
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}
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void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj)
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{
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MapIter mi;
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@ -709,7 +721,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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netlist = nl;
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if (design->has(module_name)) {
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if (!nl->IsOperator())
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if (!nl->IsOperator() && !is_blackbox(nl))
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log_cmd_error("Re-definition of module `%s'.\n", nl->Owner()->Name());
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return;
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}
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@ -718,7 +730,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
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module->name = module_name;
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design->add(module);
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if (nl->IsBlackBox()) {
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if (is_blackbox(nl)) {
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log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name));
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module->set_bool_attribute("\\blackbox");
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} else {
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