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Improve Verific importer blackbox handling 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-10-07 19:48:42 +02:00 committed by Jim Lawson
parent 8e13f2913d
commit 3bb9288d65
1 changed files with 14 additions and 2 deletions
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16
frontends/verific/verific.cc
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@ -118,6 +118,18 @@ RTLIL::SigBit VerificImporter::net_map_at(Net *net)
return net_map.at(net); return net_map.at(net);
} }
bool is_blackbox(Netlist *nl)
{
if (nl->IsBlackBox())
return true;
const char *attr = nl->GetAttValue("blackbox");
if (attr != nullptr && strcmp(attr, "0"))
return true;
return false;
}
void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj) void VerificImporter::import_attributes(dict<RTLIL::IdString, RTLIL::Const> &attributes, DesignObj *obj)
{ {
MapIter mi; MapIter mi;
@ -709,7 +721,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
netlist = nl; netlist = nl;
if (design->has(module_name)) { if (design->has(module_name)) {
if (!nl->IsOperator()) if (!nl->IsOperator() && !is_blackbox(nl))
log_cmd_error("Re-definition of module `%s'.\n", nl->Owner()->Name()); log_cmd_error("Re-definition of module `%s'.\n", nl->Owner()->Name());
return; return;
} }
@ -718,7 +730,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::se
module->name = module_name; module->name = module_name;
design->add(module); design->add(module);
if (nl->IsBlackBox()) { if (is_blackbox(nl)) {
log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name)); log("Importing blackbox module %s.\n", RTLIL::id2cstr(module->name));
module->set_bool_attribute("\\blackbox"); module->set_bool_attribute("\\blackbox");
} else { } else {