mirror of https://github.com/YosysHQ/yosys.git
Some improvements in opt_rmdff
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parent
63e6a35ce2
commit
3b8882ae49
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@ -25,6 +25,7 @@
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#include <stdio.h>
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static SigMap assign_map;
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static SigSet<RTLIL::Cell*> mux_drivers;
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static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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{
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@ -72,13 +73,36 @@ static bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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assign_map.apply(sig_c);
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assign_map.apply(sig_r);
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if (dff->type == "$dff" && mux_drivers.has(sig_d)) {
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std::set<RTLIL::Cell*> muxes;
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mux_drivers.find(sig_d, muxes);
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for (auto mux : muxes) {
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RTLIL::SigSpec sig_a = assign_map(mux->connections.at("\\A"));
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RTLIL::SigSpec sig_b = assign_map(mux->connections.at("\\B"));
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if (sig_a == sig_q && sig_b.is_fully_const()) {
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RTLIL::SigSig conn(sig_q, sig_b);
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mod->connections.push_back(conn);
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goto delete_dff;
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}
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if (sig_b == sig_q && sig_a.is_fully_const()) {
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RTLIL::SigSig conn(sig_q, sig_a);
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mod->connections.push_back(conn);
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goto delete_dff;
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}
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}
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}
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if (sig_d.is_fully_const() && sig_r.width == 0) {
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RTLIL::SigSig conn(sig_q, sig_d);
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mod->connections.push_back(conn);
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goto delete_dff;
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}
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if (sig_d == sig_q && sig_r.width == 0) {
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if (sig_d == sig_q) {
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if (sig_r.width > 0) {
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RTLIL::SigSig conn(sig_q, val_rv);
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mod->connections.push_back(conn);
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}
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goto delete_dff;
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}
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@ -117,9 +141,15 @@ struct OptRmdffPass : public Pass {
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continue;
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assign_map.set(mod_it.second);
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mux_drivers.clear();
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std::vector<std::string> dff_list;
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for (auto &it : mod_it.second->cells) {
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if (it.second->type == "$mux" || it.second->type == "$pmux") {
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if (it.second->connections.at("\\A").width == it.second->connections.at("\\B").width)
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mux_drivers.insert(assign_map(it.second->connections.at("\\Y")), it.second);
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continue;
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}
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if (!design->selected(mod_it.second, it.second))
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continue;
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if (it.second->type == "$_DFF_N_") dff_list.push_back(it.first);
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@ -144,6 +174,7 @@ struct OptRmdffPass : public Pass {
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}
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assign_map.clear();
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mux_drivers.clear();
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log("Replaced %d DFF cells.\n", total_count);
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}
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} OptRmdffPass;
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