mirror of https://github.com/YosysHQ/yosys.git
Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -3237,7 +3237,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
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remove(width, width_ - width);
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remove(width, width_ - width);
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if (width_ < width) {
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if (width_ < width) {
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RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::S0;
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RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
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if (!is_signed)
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if (!is_signed)
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padding = RTLIL::State::S0;
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padding = RTLIL::State::S0;
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while (width_ < width)
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while (width_ < width)
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@ -546,6 +546,14 @@ struct RTLIL::Const
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return ret;
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return ret;
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}
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}
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void extu(int width) {
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bits.resize(width, RTLIL::State::S0);
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}
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void exts(int width) {
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bits.resize(width, bits.empty() ? RTLIL::State::Sx : bits.back());
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}
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inline unsigned int hash() const {
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inline unsigned int hash() const {
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unsigned int h = mkhash_init;
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unsigned int h = mkhash_init;
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for (auto b : bits)
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for (auto b : bits)
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