now ignore init attributes on non-register wires in sat command

passes/sat/sat.cc

@@ -103,10 +103,30 @@ struct SatHelper
 			RTLIL::SigSpec rhs = it.second->attributes.at("\\init");
 			log_assert(lhs.width == rhs.width);
 
-			log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs));
+			RTLIL::SigSpec removed_bits;
-			big_lhs.remove2(lhs, &big_rhs);
+			for (int i = 0; i < lhs.width; i++) {
-			big_lhs.append(lhs);
+				RTLIL::SigSpec bit = lhs.extract(i, 1);
-			big_rhs.append(rhs);
+				if (!satgen.initial_state.check_all(bit)) {
+					removed_bits.append(bit);
+					lhs.remove(i, 1);
+					rhs.remove(i, 1);
+					i--;
+				}
+			}
+
+			lhs.optimize();
+			rhs.optimize();
+			removed_bits.optimize();
+
+			if (removed_bits.width)
+				log("Warning: ignoring initial value on non-register: %s\n", log_signal(removed_bits));
+
+			if (lhs.width) {
+				log("Import set-constraint from init attribute: %s = %s\n", log_signal(lhs), log_signal(rhs));
+				big_lhs.remove2(lhs, &big_rhs);
+				big_lhs.append(lhs);
+				big_rhs.append(rhs);
+			}
 		}
 
 		for (auto &s : sets_init)

tests/sat/initval.v

@@ -0,0 +1,15 @@
+module test(input clk, input [3:0] bar, output [3:0] foo);
+  reg [3:0] foo = 0;
+  reg [3:0] last_bar = 0;
+
+  always @*
+    foo[1:0] <= bar[1:0];
+
+  always @(posedge clk)
+    foo[3:2] <= bar[3:2];
+
+  always @(posedge clk)
+    last_bar <= bar;
+
+  assert property (foo == {last_bar[3:2], bar[1:0]});
+endmodule

tests/sat/initval.ys

@@ -0,0 +1,4 @@
+read_verilog -sv initval.v
+proc;;
+
+sat -seq 10 -prove-asserts