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Merge pull request #742 from whitequark/changelog 

Update CHANGELOG to mention my improvements
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Clifford Wolf 2018-12-17 16:35:56 +01:00 committed by GitHub
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commit 3b4290a1b8
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@ -9,6 +9,13 @@ Yosys 0.8 .. Yosys 0.8-dev
* Various * Various
- Added $changed support to read_verilog - Added $changed support to read_verilog
- Added "write_edif -attrprop" - Added "write_edif -attrprop"
- Added "ice40_unlut" pass
- Added "opt_lut" pass
- Added "synth_ice40 -relut"
- Added "synth_ice40 -noabc"
- Added "gate2lut.v" techmap rule
- Added "rename -src"
- Added "equiv_opt" pass
Yosys 0.7 .. Yosys 0.8 Yosys 0.7 .. Yosys 0.8