mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1111 from acw1251/help_summary_fixes
Fixed the help summary line for a few commands
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commit
3b1e5264d8
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@ -23,7 +23,7 @@ USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct BlackboxPass : public Pass {
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BlackboxPass() : Pass("blackbox", "change type of cells in the design") { }
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BlackboxPass() : Pass("blackbox", "convert modules into blackbox modules") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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@ -180,7 +180,7 @@ struct AssertpmuxWorker
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};
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struct AssertpmuxPass : public Pass {
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AssertpmuxPass() : Pass("assertpmux", "convert internal signals to module ports") { }
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AssertpmuxPass() : Pass("assertpmux", "adds asserts for parallel muxes") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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@ -195,8 +195,8 @@ struct AssertpmuxPass : public Pass {
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log("\n");
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log(" -always\n");
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log(" usually the $pmux condition is only checked when the $pmux output\n");
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log(" is used be the mux tree it drives. this option will deactivate this\n");
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log(" additional constrained and check the $pmux condition always.\n");
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log(" is used by the mux tree it drives. this option will deactivate this\n");
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log(" additional constraint and check the $pmux condition always.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -24,7 +24,7 @@ USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct CutpointPass : public Pass {
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CutpointPass() : Pass("cutpoint", "add hi/lo cover cells for each wire bit") { }
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CutpointPass() : Pass("cutpoint", "adds formal cut points to the design") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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@ -74,7 +74,7 @@ static void run_ice40_unlut(Module *module)
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}
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struct Ice40UnlutPass : public Pass {
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Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: perform simple optimizations") { }
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Ice40UnlutPass() : Pass("ice40_unlut", "iCE40: transform SB_LUT4 cells to $lut cells") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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