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Adjusting Vivado's BRAM min bits threshold for RAMB18E1

This commit is contained in:
Diego H 2019-11-26 17:14:41 -06:00
parent 0466c48533
commit 3a5a65829c
1 changed files with 5 additions and 2 deletions
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7
techlibs/xilinx/xc7_xcu_brams.txt
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@ -81,7 +81,7 @@ match $__XILINX_RAMB36_SDP
endmatch endmatch
match $__XILINX_RAMB18_SDP match $__XILINX_RAMB18_SDP
min bits 4096 min bits 1024
min efficiency 5 min efficiency 5
shuffle_enable B shuffle_enable B
make_transp make_transp
@ -97,9 +97,12 @@ match $__XILINX_RAMB36_TDP
endmatch endmatch
match $__XILINX_RAMB18_TDP match $__XILINX_RAMB18_TDP
min bits 4096 min bits 1024
min efficiency 5 min efficiency 5
shuffle_enable B shuffle_enable B
make_transp make_transp
endmatch endmatch
# [[CITE]] 7 Series FPGAs Memory Resources User Guide (UG473),
# v1.14 ed., p 29-30, July, 2019.