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CMake: add pmgen

This commit is contained in:
Miodrag Milanovic 2025-02-12 17:53:12 +01:00
parent e594e90293
commit 3a4d609060
4 changed files with 85 additions and 3 deletions
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2
CMakeLists.txt
View File

@ -61,7 +61,7 @@ add_subdirectory(passes/fsm)
add_subdirectory(passes/hierarchy)
add_subdirectory(passes/memory)
add_subdirectory(passes/opt)
#add_subdirectory(passes/pmgen)
add_subdirectory(passes/pmgen)
add_subdirectory(passes/proc)
add_subdirectory(passes/sat)
add_subdirectory(passes/techmap)

69
passes/pmgen/CMakeLists.txt Normal file
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@ -0,0 +1,69 @@
add_library(yosys_passes_pmgen INTERFACE)
function(pmgen_command _name)
add_custom_command(
OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${_name}_pm.h
COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py -o ${CMAKE_CURRENT_BINARY_DIR}/${_name}_pm.h -p ${_name} ${CMAKE_CURRENT_SOURCE_DIR}/${_name}.pmg
DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py ${CMAKE_CURRENT_SOURCE_DIR}/${_name}.pmg
COMMENT "Generating passes/pmgen/${_name}_pm.h..."
)
endfunction()
pmgen_command(test_pmgen)
pmgen_command(ice40_dsp)
pmgen_command(ice40_wrapcarry)
pmgen_command(xilinx_dsp)
pmgen_command(xilinx_dsp48a)
pmgen_command(xilinx_dsp_CREG)
pmgen_command(xilinx_dsp_cascade)
pmgen_command(microchip_dsp)
pmgen_command(microchip_dsp_CREG)
pmgen_command(microchip_dsp_cascade)
pmgen_command(xilinx_srl)
add_custom_command(
OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/peepopt_pm.h
COMMAND ${Python3_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py -o ${CMAKE_CURRENT_BINARY_DIR}/peepopt_pm.h -p peepopt
${CMAKE_CURRENT_SOURCE_DIR}/peepopt_shiftmul_right.pmg
${CMAKE_CURRENT_SOURCE_DIR}/peepopt_shiftmul_left.pmg
${CMAKE_CURRENT_SOURCE_DIR}/peepopt_shiftadd.pmg
${CMAKE_CURRENT_SOURCE_DIR}/peepopt_muldiv.pmg
${CMAKE_CURRENT_SOURCE_DIR}/peepopt_formal_clockgateff.pmg
DEPENDS ${CMAKE_CURRENT_SOURCE_DIR}/pmgen.py
${CMAKE_CURRENT_SOURCE_DIR}/peepopt_shiftmul_right.pmg
${CMAKE_CURRENT_SOURCE_DIR}/peepopt_shiftmul_left.pmg
${CMAKE_CURRENT_SOURCE_DIR}/peepopt_shiftadd.pmg
${CMAKE_CURRENT_SOURCE_DIR}/peepopt_muldiv.pmg
${CMAKE_CURRENT_SOURCE_DIR}/peepopt_formal_clockgateff.pmg
COMMENT "Generating passes/pmgen/peepopt_pm.h..."
)
target_sources(yosys_passes_pmgen INTERFACE
test_pmgen.cc
ice40_dsp.cc
ice40_wrapcarry.cc
xilinx_dsp.cc
microchip_dsp.cc
peepopt.cc
xilinx_srl.cc
)
target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/test_pmgen_pm.h)
target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/ice40_dsp_pm.h)
target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/ice40_wrapcarry_pm.h)
target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/xilinx_dsp_pm.h)
target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/xilinx_dsp48a_pm.h)
target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/xilinx_dsp_CREG_pm.h)
target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/xilinx_dsp_cascade_pm.h)
target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/microchip_dsp_pm.h)
target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/microchip_dsp_CREG_pm.h)
target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/microchip_dsp_cascade_pm.h)
target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/peepopt_pm.h)
target_sources(yosys_passes_pmgen PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/xilinx_srl_pm.h)
target_link_libraries(yosys PRIVATE yosys_passes_pmgen)

15
techlibs/quicklogic/CMakeLists.txt
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@ -1,12 +1,25 @@
add_library(yosys_techlibs_quicklogic INTERFACE)
function(pmgen_command _name)
add_custom_command(
OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${_name}_pm.h
COMMAND ${Python3_EXECUTABLE} ${CMAKE_SOURCE_DIR}/passes/pmgen/pmgen.py -o ${CMAKE_CURRENT_BINARY_DIR}/${_name}_pm.h -p ${_name} ${CMAKE_CURRENT_SOURCE_DIR}/${_name}.pmg
DEPENDS ${CMAKE_SOURCE_DIR}/passes/pmgen/pmgen.py ${CMAKE_CURRENT_SOURCE_DIR}/${_name}.pmg
COMMENT "Generating passes/pmgen/${_name}_pm.h..."
)
endfunction()
pmgen_command(ql_dsp_macc)
target_sources(yosys_techlibs_quicklogic INTERFACE
synth_quicklogic.cc
ql_bram_merge.cc
ql_bram_types.cc
ql_dsp_simd.cc
ql_dsp_io_regs.cc
#ql_dsp_macc.cc
ql_dsp_macc.cc
)
target_sources(yosys_techlibs_quicklogic PRIVATE ${CMAKE_CURRENT_BINARY_DIR}/ql_dsp_macc_pm.h)
target_link_libraries(yosys PRIVATE yosys_techlibs_quicklogic)