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Updated PGEN model to have level triggered reset (matches actual hardware behavior

This commit is contained in:
Andrew Zonenberg 2017-08-14 17:15:56 -07:00
parent e5109847c9
commit 3a404be62a
1 changed files with 4 additions and 4 deletions
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8
techlibs/greenpak4/cells_sim_digital.v
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@ -741,10 +741,10 @@ module GP_PGEN(input wire nRST, input wire CLK, output reg OUT);
localparam COUNT_MAX = PATTERN_LEN - 1'h1; localparam COUNT_MAX = PATTERN_LEN - 1'h1;
reg[3:0] count = 0; reg[3:0] count = 0;
always @(posedge CLK) begin always @(posedge CLK, negedge nRST) begin
if(!nRST) begin
count <= COUNT_MAX; if(!nRST)
end count <= 0;
else begin else begin
count <= count - 1'h1; count <= count - 1'h1;