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Set more ports explicitly

This commit is contained in:
Eddie Hung 2019-09-12 17:10:43 -07:00
parent a1123b095c
commit 3a39073302
2 changed files with 4 additions and 1 deletions
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2
passes/pmgen/xilinx_dsp.cc
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@ -44,6 +44,8 @@ static Cell* addDsp(Module *module) {
cell->setParam("\\OPMODEREG", 0); cell->setParam("\\OPMODEREG", 0);
cell->setParam("\\PREG", 0); cell->setParam("\\PREG", 0);
cell->setParam("\\USE_MULT", Const("NONE")); cell->setParam("\\USE_MULT", Const("NONE"));
cell->setParam("\\USE_SIMD", Const("ONE48"));
cell->setParam("\\USE_DPORT", Const("FALSE"));
cell->setPort("\\D", Const(0, 24)); cell->setPort("\\D", Const(0, 24));
cell->setPort("\\INMODE", Const(0, 5)); cell->setPort("\\INMODE", Const(0, 5));

3
techlibs/xilinx/dsp_map.v
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@ -25,7 +25,8 @@ module \$__MUL25X18 (input [24:0] A, input [17:0] B, output [42:0] Y);
.OPMODEREG(0), .OPMODEREG(0),
.PREG(0), .PREG(0),
.USE_MULT("MULTIPLY"), .USE_MULT("MULTIPLY"),
.USE_SIMD("ONE48") .USE_SIMD("ONE48"),
.USE_DPORT("FALSE")
) _TECHMAP_REPLACE_ ( ) _TECHMAP_REPLACE_ (
//Data path //Data path
.A({{5{A[24]}}, A}), .A({{5{A[24]}}, A}),