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ecp5: Fixing miscellaneous sim model issues 

Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-07-16 15:56:12 +02:00
parent e9ef077266
commit 3a3558acce
1 changed files with 2 additions and 2 deletions
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4
techlibs/ecp5/cells_sim.v
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@ -232,13 +232,13 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
always @(posedge muxclk, posedge muxlsr) always @(posedge muxclk, posedge muxlsr)
if (muxlsr) if (muxlsr)
Q <= srval; Q <= srval;
else else if (muxce)
Q <= DI; Q <= DI;
end else begin end else begin
always @(posedge muxclk) always @(posedge muxclk)
if (muxlsr) if (muxlsr)
Q <= srval; Q <= srval;
else else if (muxce)
Q <= DI; Q <= DI;
end end
endgenerate endgenerate