diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index cf1446a52..1700694e8 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -232,13 +232,13 @@ module TRELLIS_FF(input CLK, LSR, CE, DI, output reg Q);
 			always @(posedge muxclk, posedge muxlsr)
 				if (muxlsr)
 					Q <= srval;
-				else
+				else if (muxce)
 					Q <= DI;
 		end else begin
 			always @(posedge muxclk)
 				if (muxlsr)
 					Q <= srval;
-				else
+				else if (muxce)
 					Q <= DI;
 		end
 	endgenerate