riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

sf2/cells_sim.v: add XTLOSC, SYSRESET cells

This commit is contained in:
Tristan Gingold 2021-11-25 09:23:22 +01:00
parent 1c0119aa90
commit 39993a92d7
1 changed files with 110 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

111
techlibs/sf2/cells_sim.v
View File

@ -157,7 +157,6 @@ endmodule
// module FCINIT_BUFF
// module FLASH_FREEZE
// module OSCILLATOR
// module SYSRESET
// module SYSCTRL_RESET_STATUS
// module LIVE_PROBE_FB
@ -453,3 +452,113 @@ endmodule
// module RAM1K18
// module RAM64x18
// module MACC
(* blackbox *)
module SYSRESET (
(* iopad_external_pin *)
input DEVRST_N,
output POWER_ON_RESET_N);
endmodule
(* blackbox *)
module XTLOSC (
(* iopad_external_pin *)
input XTL,
output CLKOUT);
parameter [1:0] MODE = 2'h3;
parameter real FREQUENCY = 20.0;
endmodule
(* blackbox *)
module RAM1K18 (
input [13:0] A_ADDR,
input [2:0] A_BLK,
(* clkbuf_sink *)
input A_CLK,
input [17:0] A_DIN,
output [17:0] A_DOUT,
input [1:0] A_WEN,
input [2:0] A_WIDTH,
input A_WMODE,
input A_ARST_N,
input A_DOUT_LAT,
input A_DOUT_ARST_N,
(* clkbuf_sink *)
input A_DOUT_CLK,
input A_DOUT_EN,
input A_DOUT_SRST_N,
input [13:0] B_ADDR,
input [2:0] B_BLK,
(* clkbuf_sink *)
input B_CLK,
input [17:0] B_DIN,
output [17:0] B_DOUT,
input [1:0] B_WEN,
input [2:0] B_WIDTH,
input B_WMODE,
input B_ARST_N,
input B_DOUT_LAT,
input B_DOUT_ARST_N,
(* clkbuf_sink *)
input B_DOUT_CLK,
input B_DOUT_EN,
input B_DOUT_SRST_N,
input A_EN,
input B_EN,
input SII_LOCK,
output BUSY);
endmodule
(* blackbox *)
module RAM64x18 (
input [9:0] A_ADDR,
input [1:0] A_BLK,
input [2:0] A_WIDTH,
output [17:0] A_DOUT,
input A_DOUT_ARST_N,
(* clkbuf_sink *)
input A_DOUT_CLK,
input A_DOUT_EN,
input A_DOUT_LAT,
input A_DOUT_SRST_N,
(* clkbuf_sink *)
input A_ADDR_CLK,
input A_ADDR_EN,
input A_ADDR_LAT,
input A_ADDR_SRST_N,
input A_ADDR_ARST_N,
input [9:0] B_ADDR,
input [1:0] B_BLK,
input [2:0] B_WIDTH,
output [17:0] B_DOUT,
input B_DOUT_ARST_N,
(* clkbuf_sink *)
input B_DOUT_CLK,
input B_DOUT_EN,
input B_DOUT_LAT,
input B_DOUT_SRST_N,
(* clkbuf_sink *)
input B_ADDR_CLK,
input B_ADDR_EN,
input B_ADDR_LAT,
input B_ADDR_SRST_N,
input B_ADDR_ARST_N,
input [9:0] C_ADDR,
(* clkbuf_sink *)
input C_CLK,
input [17:0] C_DIN,
input C_WEN,
input [1:0] C_BLK,
input [2:0] C_WIDTH,
input A_EN,
input B_EN,
input C_EN,
input SII_LOCK,
output BUSY);
endmodule