Add ability to blackbox modules/units from file while reading with verific

frontends/verific/verific.cc

@@ -1197,13 +1197,13 @@ static std::string sha1_if_contain_spaces(std::string str)
 
 void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::map<std::string,Netlist*> &nl_todo, bool norename)
 {
-	std::string netlist_name = nl->GetAtt(" \\top") ? nl->CellBaseName() : nl->Owner()->Name();
+	std::string netlist_name = nl->GetAtt(" \\top") || is_blackbox(nl) ? nl->CellBaseName() : nl->Owner()->Name();
 	std::string module_name = netlist_name;
 
 	if (nl->IsOperator() || nl->IsPrimitive()) {
 		module_name = "$verific$" + module_name;
 	} else {
-		if (!norename && *nl->Name()) {
+		if (!norename && *nl->Name() && !is_blackbox(nl)) {
 			module_name += "(";
 			module_name += nl->Name();
 			module_name += ")";
@@ -1893,14 +1893,14 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		}
 
 	import_verific_cells:
-		std::string inst_type = inst->View()->Owner()->Name();
+		std::string inst_type = is_blackbox(inst->View()) ? inst->View()->CellBaseName() : inst->View()->Owner()->Name();
 
 		nl_todo[inst_type] = inst->View();
 
 		if (inst->View()->IsOperator() || inst->View()->IsPrimitive()) {
 			inst_type = "$verific$" + inst_type;
 		} else {
-			if (*inst->View()->Name()) {
+			if (*inst->View()->Name() && !is_blackbox(inst->View())) {
 				inst_type += "(";
 				inst_type += inst->View()->Name();
 				inst_type += ")";
@@ -1918,6 +1918,14 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		if (verific_verbose)
 			log("    ports in verific db:\n");
 
+        const char *param_name ;
+        const char *param_value ;
+		if (is_blackbox(inst->View())) {
+        	FOREACH_PARAMETER_OF_INST(inst, mi2, param_name, param_value) {
+				cell->setParam(RTLIL::escape_id(param_name), verific_const(param_value));
+			}
+		}
+
 		FOREACH_PORTREF_OF_INST(inst, mi2, pr) {
 			if (verific_verbose)
 				log("      .%s(%s)\n", pr->GetPort()->Name(), pr->GetNet()->Name());
@@ -2834,6 +2842,67 @@ struct VerificPass : public Pass {
 		return filename;
 	}
 
+#ifdef VERIFIC_VHDL_SUPPORT
+	void add_units_to_map(Map &map, std::string work, bool flag_lib)
+	{
+		MapIter mi ;
+		VhdlPrimaryUnit *unit ;
+		if (flag_lib) {
+			VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
+			if (vhdl_lib) {					
+				FOREACH_VHDL_PRIMARY_UNIT(vhdl_lib, mi, unit) {
+					if (!unit) continue;
+					map.Insert(unit,unit);
+				}
+			}
+		}
+	}
+
+	void set_units_to_blackbox(Map &map, std::string work, bool flag_lib)
+	{
+		MapIter mi ;
+		VhdlPrimaryUnit *unit ;
+		if (!flag_lib) return;
+		VhdlLibrary *vhdl_lib = vhdl_file::GetLibrary(work.c_str(), 1);
+		FOREACH_VHDL_PRIMARY_UNIT(vhdl_lib, mi, unit) {
+			if (!unit) continue;
+			if (!map.GetValue(unit)) {
+				unit->SetCompileAsBlackbox();
+			}
+		}
+	}
+#endif
+
+	void add_modules_to_map(Map &map, std::string work, bool flag_lib)
+	{
+		MapIter mi ;
+		VeriModule *veri_module ;
+		if (flag_lib) {
+
+			VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
+			if (veri_lib) {					
+				FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
+					if (!veri_module) continue;
+					map.Insert(veri_module,veri_module);
+				}
+			}
+		}
+	}
+
+	void set_modules_to_blackbox(Map &map, std::string work, bool flag_lib)
+	{
+		MapIter mi ;
+		VeriModule *veri_module ;
+		if (!flag_lib) return;
+		VeriLibrary *veri_lib = veri_file::GetLibrary(work.c_str(), 1);
+		FOREACH_VERILOG_MODULE_IN_LIBRARY(veri_lib, mi, veri_module) {
+			if (!veri_module) continue;
+			if (!map.GetValue(veri_module)) {
+				veri_module->SetCompileAsBlackbox();
+			}
+		}
+	}
+
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		static bool set_verific_global_flags = true;
@@ -3130,15 +3199,27 @@ struct VerificPass : public Pass {
 			for (auto &ext : verific_libexts)
 				veri_file::AddLibExt(ext.c_str());
 
+			bool flag_lib = false;
 			while (argidx < GetSize(args)) {
+				if (args[argidx] == "-lib") {
+					flag_lib = true;
+					argidx++;
+					continue;
+				}
+				if (args[argidx].compare(0, 1, "-") == 0) {
+					cmd_error(args, argidx, "unknown option");
+					goto check_error;
+				}
 				std::string filename = frontent_rewrite(args, argidx, tmp_files);
 				file_names.Insert(strdup(filename.c_str()));
 			}
+			Map map(POINTER_HASH);
+			add_modules_to_map(map, work, flag_lib);
 			if (!veri_file::AnalyzeMultipleFiles(&file_names, verilog_mode, work.c_str(), veri_file::MFCU)) {
 					verific_error_msg.clear();
 					log_cmd_error("Reading Verilog/SystemVerilog sources failed.\n");
 			}
-
+			set_modules_to_blackbox(map, work, flag_lib);
 			verific_import_pending = true;
 			goto check_error;
 		}
@@ -3146,11 +3227,22 @@ struct VerificPass : public Pass {
 #ifdef VERIFIC_VHDL_SUPPORT
 		if (GetSize(args) > argidx && args[argidx] == "-vhdl87") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1987").c_str());
-			argidx++;
+			bool flag_lib = false;
-			while (argidx < GetSize(args)) {
+			for (argidx++; argidx < GetSize(args); argidx++) {
+				if (args[argidx] == "-lib") {
+					flag_lib = true;
+					continue;
+				}
+				if (args[argidx].compare(0, 1, "-") == 0) {
+					cmd_error(args, argidx, "unknown option");
+					goto check_error;
+				}
+				Map map(POINTER_HASH);
+				add_units_to_map(map, work, flag_lib);
 				std::string filename = frontent_rewrite(args, argidx, tmp_files);
 				if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_87))
 					log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", filename.c_str());
+				set_units_to_blackbox(map, work, flag_lib);
 			}
 			verific_import_pending = true;
 			goto check_error;
@@ -3158,11 +3250,22 @@ struct VerificPass : public Pass {
 
 		if (GetSize(args) > argidx && args[argidx] == "-vhdl93") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
-			argidx++;
+			bool flag_lib = false;
-			while (argidx < GetSize(args)) {
+			for (argidx++; argidx < GetSize(args); argidx++) {
+				if (args[argidx] == "-lib") {
+					flag_lib = true;
+					continue;
+				}
+				if (args[argidx].compare(0, 1, "-") == 0) {
+					cmd_error(args, argidx, "unknown option");
+					goto check_error;
+				}
+				Map map(POINTER_HASH);
+				add_units_to_map(map, work, flag_lib);
 				std::string filename = frontent_rewrite(args, argidx, tmp_files);
 				if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_93))
 					log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", filename.c_str());
+				set_units_to_blackbox(map, work, flag_lib);
 			}
 			verific_import_pending = true;
 			goto check_error;
@@ -3170,11 +3273,22 @@ struct VerificPass : public Pass {
 
 		if (GetSize(args) > argidx && args[argidx] == "-vhdl2k") {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_1993").c_str());
-			argidx++;
+			bool flag_lib = false;
-			while (argidx < GetSize(args)) {
+			for (argidx++; argidx < GetSize(args); argidx++) {
+				if (args[argidx] == "-lib") {
+					flag_lib = true;
+					continue;
+				}
+				if (args[argidx].compare(0, 1, "-") == 0) {
+					cmd_error(args, argidx, "unknown option");
+					goto check_error;
+				}
+				Map map(POINTER_HASH);
+				add_units_to_map(map, work, flag_lib);
 				std::string filename = frontent_rewrite(args, argidx, tmp_files);
 				if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2K))
 					log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", filename.c_str());
+				set_units_to_blackbox(map, work, flag_lib);
 			}
 			verific_import_pending = true;
 			goto check_error;
@@ -3182,11 +3296,22 @@ struct VerificPass : public Pass {
 
 		if (GetSize(args) > argidx && (args[argidx] == "-vhdl2008" || args[argidx] == "-vhdl")) {
 			vhdl_file::SetDefaultLibraryPath((proc_share_dirname() + "verific/vhdl_vdbs_2008").c_str());
-			argidx++;
+			bool flag_lib = false;
-			while (argidx < GetSize(args)) {
+			for (argidx++; argidx < GetSize(args); argidx++) {
+				if (args[argidx] == "-lib") {
+					flag_lib = true;
+					continue;
+				}
+				if (args[argidx].compare(0, 1, "-") == 0) {
+					cmd_error(args, argidx, "unknown option");
+					goto check_error;
+				}
+				Map map(POINTER_HASH);
+				add_units_to_map(map, work, flag_lib);
 				std::string filename = frontent_rewrite(args, argidx, tmp_files);
 				if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2008))
 					log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", filename.c_str());
+				set_units_to_blackbox(map, work, flag_lib);
 			}
 			verific_import_pending = true;
 			goto check_error;