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Merge pull request #4851 from YosysHQ/nak/scopeindex_private_hdlname 

handle some cases of hdlname attribute on private objects
This commit is contained in:
N. Engelhardt 2025-01-20 14:12:25 +00:00 committed by GitHub
parent 76d85fefac a5ba1d2eba
commit 398024e813
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GPG Key ID: B5690EEEBB952194
3 changed files with 28 additions and 6 deletions
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1
frontends/verific/verific.cc
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@ -1464,6 +1464,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
log("Importing module %s.\n", RTLIL::id2cstr(module->name)); log("Importing module %s.\n", RTLIL::id2cstr(module->name));
} }
import_attributes(module->attributes, nl, nl); import_attributes(module->attributes, nl, nl);
if (module->name.isPublic())
module->set_string_attribute(ID::hdlname, nl->CellBaseName()); module->set_string_attribute(ID::hdlname, nl->CellBaseName());
module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name()); module->set_string_attribute(ID(library), nl->Owner()->Owner()->Name());
#ifdef VERIFIC_VHDL_SUPPORT #ifdef VERIFIC_VHDL_SUPPORT

17
kernel/scopeinfo.h
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@ -337,12 +337,14 @@ template<typename O>
std::vector<IdString> parse_hdlname(const O* object) std::vector<IdString> parse_hdlname(const O* object)
{ {
std::vector<IdString> path; std::vector<IdString> path;
if (!object->name.isPublic())
return path;
for (auto const &item : object->get_hdlname_attribute()) for (auto const &item : object->get_hdlname_attribute())
path.push_back("\\" + item); path.push_back("\\" + item);
if (path.empty()) if (path.empty() && object->name.isPublic())
path.push_back(object->name); path.push_back(object->name);
if (!path.empty() && !(object->name.isPublic() || object->name.begins_with("$paramod") || object->name.begins_with("$abstract"))) {
path.pop_back();
path.push_back(object->name);
}
return path; return path;
} }
@ -351,17 +353,22 @@ std::pair<std::vector<IdString>, IdString> parse_scopename(const O* object)
{ {
std::vector<IdString> path; std::vector<IdString> path;
IdString trailing = object->name; IdString trailing = object->name;
if (object->name.isPublic()) { if (object->name.isPublic() || object->name.begins_with("$paramod") || object->name.begins_with("$abstract")) {
for (auto const &item : object->get_hdlname_attribute()) for (auto const &item : object->get_hdlname_attribute())
path.push_back("\\" + item); path.push_back("\\" + item);
if (!path.empty()) { if (!path.empty()) {
trailing = path.back(); trailing = path.back();
path.pop_back(); path.pop_back();
} }
} else if (object->has_attribute(ID::hdlname)) {
for (auto const &item : object->get_hdlname_attribute())
path.push_back("\\" + item);
if (!path.empty()) {
path.pop_back();
}
} else { } else {
for (auto const &item : split_tokens(object->get_string_attribute(ID(scopename)), " ")) for (auto const &item : split_tokens(object->get_string_attribute(ID(scopename)), " "))
path.push_back("\\" + item); path.push_back("\\" + item);
} }
return {path, trailing}; return {path, trailing};
} }

14
passes/fsm/fsm_extract.cc
View File

@ -377,6 +377,13 @@ static void extract_fsm(RTLIL::Wire *wire)
fsm_cell->setPort(ID::CTRL_OUT, ctrl_out); fsm_cell->setPort(ID::CTRL_OUT, ctrl_out);
fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str()); fsm_cell->parameters[ID::NAME] = RTLIL::Const(wire->name.str());
fsm_cell->attributes = wire->attributes; fsm_cell->attributes = wire->attributes;
if(fsm_cell->attributes.count(ID::hdlname)) {
auto hdlname = fsm_cell->get_hdlname_attribute();
hdlname.pop_back();
fsm_cell->set_hdlname_attribute(hdlname);
fsm_cell->set_string_attribute(ID(scopename), fsm_cell->get_string_attribute(ID::hdlname));
fsm_cell->attributes.erase(ID::hdlname);
}
fsm_data.copy_to_cell(fsm_cell); fsm_data.copy_to_cell(fsm_cell);
// rename original state wire // rename original state wire
@ -385,6 +392,13 @@ static void extract_fsm(RTLIL::Wire *wire)
wire->attributes.erase(ID::fsm_encoding); wire->attributes.erase(ID::fsm_encoding);
wire->name = stringf("$fsm$oldstate%s", wire->name.c_str()); wire->name = stringf("$fsm$oldstate%s", wire->name.c_str());
module->wires_[wire->name] = wire; module->wires_[wire->name] = wire;
if(wire->attributes.count(ID::hdlname)) {
auto hdlname = wire->get_hdlname_attribute();
hdlname.pop_back();
wire->set_hdlname_attribute(hdlname);
wire->set_string_attribute(ID(scopename), wire->get_string_attribute(ID::hdlname));
wire->attributes.erase(ID::hdlname);
}
// unconnect control outputs from old drivers // unconnect control outputs from old drivers