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Merge pull request #3001 from YosysHQ/claire/sigcheck 

Add additional check to SigSpec
This commit is contained in:
Miodrag Milanović 2021-09-10 17:32:04 +02:00 committed by GitHub
parent 33749f1e3a 4708907be8
commit 396918cc30
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 14 additions and 6 deletions
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16
kernel/rtlil.cc
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@ -1753,7 +1753,7 @@ void RTLIL::Module::check()
log_assert(!it.second->type.empty());
for (auto &it2 : it.second->connections()) {
log_assert(!it2.first.empty());
it2.second.check();
it2.second.check(this);
}
for (auto &it2 : it.second->attributes)
log_assert(!it2.first.empty());
@ -1799,8 +1799,8 @@ void RTLIL::Module::check()
for (auto &it : connections_) {
log_assert(it.first.size() == it.second.size());
log_assert(!it.first.has_const());
it.first.check();
it.second.check();
it.first.check(this);
it.second.check(this);
}
for (auto &it : attributes)
@ -4130,7 +4130,7 @@ RTLIL::SigSpec RTLIL::SigSpec::repeat(int num) const
}
#ifndef NDEBUG
void RTLIL::SigSpec::check() const
void RTLIL::SigSpec::check(Module *mod) const
{
if (width_ > 64)
{
@ -4156,6 +4156,8 @@ void RTLIL::SigSpec::check() const
log_assert(chunk.width >= 0);
log_assert(chunk.offset + chunk.width <= chunk.wire->width);
log_assert(chunk.data.size() == 0);
if (mod != nullptr)
log_assert(chunk.wire->module == mod);
}
w += chunk.width;
}
@ -4166,6 +4168,12 @@ void RTLIL::SigSpec::check() const
{
cover("kernel.rtlil.sigspec.check.unpacked");
if (mod != nullptr) {
for (size_t i = 0; i < bits_.size(); i++)
if (bits_[i].wire != nullptr)
log_assert(bits_[i].wire->module == mod);
}
log_assert(width_ == GetSize(bits_));
log_assert(chunks_.empty());
}

4
kernel/rtlil.h
View File

@ -965,9 +965,9 @@ public:
unsigned int hash() const { if (!hash_) updhash(); return hash_; };
#ifndef NDEBUG
void check() const;
void check(Module *mod = nullptr) const;
#else
void check() const { }
void check(Module *mod = nullptr) const { }
#endif
};