From 433b0c677c16ef5cc2fa92c576c54cc1a3a09f7f Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 4 Sep 2019 13:42:44 -0700 Subject: [PATCH 1/5] Remove log_cell() calls --- passes/pmgen/peepopt_dffmuxext.pmg | 3 --- 1 file changed, 3 deletions(-) diff --git a/passes/pmgen/peepopt_dffmuxext.pmg b/passes/pmgen/peepopt_dffmuxext.pmg index e99ce1602..2465d6171 100644 --- a/passes/pmgen/peepopt_dffmuxext.pmg +++ b/passes/pmgen/peepopt_dffmuxext.pmg @@ -22,9 +22,6 @@ endmatch code did_something = true; - log_cell(dff); - log_cell(mux); - SigSpec &D = mux->connections_.at(muxAB); SigSpec &Q = dff->connections_.at(\Q); int width = GetSize(D); From 6fe1ca633d90fb238d2671dba3d7f772c263a497 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 4 Sep 2019 15:20:04 -0700 Subject: [PATCH 2/5] abc9 followed by clean otherwise netlist could be invalid for sim --- tests/simple_abc9/run-test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 0d4262005..4d15a3253 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -25,5 +25,6 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p '\ synth -run coarse; \ opt -full; \ techmap; abc9 -lut 4 -box ../abc.box; \ + clean; \ check -assert; \ select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" From d3eea82bc27f6e54b6c1e05a73be8456344ec8b7 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Wed, 4 Sep 2019 15:21:39 -0700 Subject: [PATCH 3/5] Revert "parse_xaiger() to do "clean -purge"" This reverts commit 5d16bf831688ff665b0ec2abd6835b71320b2db5. --- frontends/aiger/aigerparse.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/frontends/aiger/aigerparse.cc b/frontends/aiger/aigerparse.cc index 2e1fb8fad..06522939f 100644 --- a/frontends/aiger/aigerparse.cc +++ b/frontends/aiger/aigerparse.cc @@ -974,7 +974,7 @@ void AigerReader::post_process() // operate (and run checks on) this one module RTLIL::Design *mapped_design = new RTLIL::Design; mapped_design->add(module); - Pass::call(mapped_design, "clean -purge"); + Pass::call(mapped_design, "clean"); mapped_design->modules_.erase(module->name); delete mapped_design; From 11f623cbe0057ee752f2545eb7100966afb08676 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 5 Sep 2019 08:25:09 -0700 Subject: [PATCH 4/5] Revert "abc9 followed by clean otherwise netlist could be invalid for sim" This reverts commit 6fe1ca633d90fb238d2671dba3d7f772c263a497. --- tests/simple_abc9/run-test.sh | 1 - 1 file changed, 1 deletion(-) diff --git a/tests/simple_abc9/run-test.sh b/tests/simple_abc9/run-test.sh index 4d15a3253..0d4262005 100755 --- a/tests/simple_abc9/run-test.sh +++ b/tests/simple_abc9/run-test.sh @@ -25,6 +25,5 @@ exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-n 300 -p '\ synth -run coarse; \ opt -full; \ techmap; abc9 -lut 4 -box ../abc.box; \ - clean; \ check -assert; \ select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'" From ef0681ea4ca0b34689cbf14d5a4478e2785600d9 Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 5 Sep 2019 08:43:22 -0700 Subject: [PATCH 5/5] simple/peepopt.v tests to various/peepopt.ys with equiv_opt & select --- tests/simple/peepopt.v | 21 -------------- tests/various/peepopt.ys | 63 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+), 21 deletions(-) delete mode 100644 tests/simple/peepopt.v create mode 100644 tests/various/peepopt.ys diff --git a/tests/simple/peepopt.v b/tests/simple/peepopt.v deleted file mode 100644 index b4d113dba..000000000 --- a/tests/simple/peepopt.v +++ /dev/null @@ -1,21 +0,0 @@ -module peepopt_shiftmul_0 #(parameter N=3, parameter W=3) (input [N*W-1:0] i, input [$clog2(N)-1:0] s, output [W-1:0] o); -assign o = i[s*W+:W]; -endmodule - -module peepopt_shiftmul_1 (output y, input [2:0] w); -assign y = 1'b1 >> (w * (3'b110)); -endmodule - -module peepopt_muldiv_0(input [1:0] i, output [1:0] o); -wire [3:0] t; -assign t = i * 3; -assign o = t / 3; -endmodule - -module peepopt_dffmuxext_signed(input clk, ce, input signed [1:0] i, output reg signed [3:0] o); - always @(posedge clk) if (ce) o <= i; -endmodule - -module peepopt_dffmuxext_unsigned(input clk, ce, input [1:0] i, output reg [3:0] o); - always @(posedge clk) if (ce) o <= i; -endmodule diff --git a/tests/various/peepopt.ys b/tests/various/peepopt.ys new file mode 100644 index 000000000..91db22423 --- /dev/null +++ b/tests/various/peepopt.ys @@ -0,0 +1,63 @@ +read_verilog <> (w * (3'b110)); +endmodule +EOT + +prep -nokeepdc +equiv_opt peepopt +design -load postopt +clean +select -assert-count 1 t:$shr +select -assert-count 1 t:$mul +select -assert-count 0 t:$shr t:$mul %% t:* %D + +#################### + +design -reset +read_verilog <