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Code Issues Projects Releases Wiki Activity

Fix #1496.

This commit is contained in:
Marcin Kościelnicki 2019-11-18 04:16:48 +01:00
parent 527434de49
commit 38e72d6e13
2 changed files with 21 additions and 4 deletions
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12
passes/techmap/extract_fa.cc
View File

@ -262,10 +262,14 @@ struct ExtractFaWorker
pool<SigBit> new_leaves = leaves; pool<SigBit> new_leaves = leaves;
new_leaves.erase(bit); new_leaves.erase(bit);
if (cell->hasPort(ID::A)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::A)))); for (auto port : {ID::A, ID::B, ID(C), ID(D)}) {
if (cell->hasPort(ID::B)) new_leaves.insert(sigmap(SigBit(cell->getPort(ID::B)))); if (!cell->hasPort(port))
if (cell->hasPort(ID(C))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(C))))); continue;
if (cell->hasPort(ID(D))) new_leaves.insert(sigmap(SigBit(cell->getPort(ID(D))))); auto bit = sigmap(SigBit(cell->getPort(port)));
if (!bit.wire)
continue;
new_leaves.insert(bit);
}
if (GetSize(new_leaves) > maxbreadth) if (GetSize(new_leaves) > maxbreadth)
continue; continue;

13
tests/various/bug1496.ys Normal file
View File

@ -0,0 +1,13 @@
read_ilang << EOF
module \top
wire input 1 \A
wire output 2 \Y
cell $_AND_ \sub
connect \A \A
connect \B 1'0
connect \Y \Y
end
end
EOF
extract_fa