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Added support for global tasks and functions

This commit is contained in:
Clifford Wolf 2014-08-21 12:42:28 +02:00
parent a92a68ce52
commit 38addd4c67
3 changed files with 49 additions and 27 deletions
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38
frontends/ast/ast.cc
View File

@ -945,21 +945,35 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
flag_icells = icells; flag_icells = icells;
flag_autowire = autowire; flag_autowire = autowire;
std::vector<AstNode*> global_decls;
log_assert(current_ast->type == AST_DESIGN); log_assert(current_ast->type == AST_DESIGN);
for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) { for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++)
if (flag_icells && (*it)->str.substr(0, 2) == "\\$") {
(*it)->str = (*it)->str.substr(1); if ((*it)->type == AST_MODULE)
if (defer) {
(*it)->str = "$abstract" + (*it)->str; for (auto n : global_decls)
if (design->has((*it)->str)) { (*it)->children.push_back(n->clone());
if (!ignore_redef)
log_error("Re-definition of module `%s' at %s:%d!\n", if (flag_icells && (*it)->str.substr(0, 2) == "\\$")
(*it)->str = (*it)->str.substr(1);
if (defer)
(*it)->str = "$abstract" + (*it)->str;
if (design->has((*it)->str)) {
if (!ignore_redef)
log_error("Re-definition of module `%s' at %s:%d!\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
log("Ignoring re-definition of module `%s' at %s:%d!\n",
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); (*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum);
log("Ignoring re-definition of module `%s' at %s:%d!\n", continue;
(*it)->str.c_str(), (*it)->filename.c_str(), (*it)->linenum); }
continue;
design->add(process_module(*it, defer));
} }
design->add(process_module(*it, defer)); else
global_decls.push_back(*it);
} }
} }

30
frontends/verilog/parser.y
View File

@ -137,14 +137,21 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%% %%
input: input: {
module input | ast_stack.push_back(current_ast);
defattr input | } design {
/* empty */ { ast_stack.pop_back();
for (auto &it : default_attr_list) log_assert(SIZE(ast_stack) == 0);
delete it.second; for (auto &it : default_attr_list)
default_attr_list.clear(); delete it.second;
}; default_attr_list.clear();
};
design:
module design |
defattr design |
task_func_decl design |
/* empty */;
attr: attr:
{ {
@ -214,9 +221,9 @@ module:
attr TOK_MODULE TOK_ID { attr TOK_MODULE TOK_ID {
do_not_require_port_stubs = false; do_not_require_port_stubs = false;
AstNode *mod = new AstNode(AST_MODULE); AstNode *mod = new AstNode(AST_MODULE);
current_ast->children.push_back(mod); ast_stack.back()->children.push_back(mod);
current_ast_mod = mod;
ast_stack.push_back(mod); ast_stack.push_back(mod);
current_ast_mod = mod;
port_stubs.clear(); port_stubs.clear();
port_counter = 0; port_counter = 0;
mod->str = *$3; mod->str = *$3;
@ -227,7 +234,8 @@ module:
frontend_verilog_yyerror("Missing details for module port `%s'.", frontend_verilog_yyerror("Missing details for module port `%s'.",
port_stubs.begin()->first.c_str()); port_stubs.begin()->first.c_str());
ast_stack.pop_back(); ast_stack.pop_back();
log_assert(ast_stack.size() == 0); log_assert(ast_stack.size() == 1);
current_ast_mod = NULL;
}; };
module_para_opt: module_para_opt:

8
frontends/verilog/verilog_frontend.cc
View File

@ -285,10 +285,10 @@ struct VerilogFrontend : public Frontend {
frontend_verilog_yylex_destroy(); frontend_verilog_yylex_destroy();
for (auto &child : current_ast->children) { for (auto &child : current_ast->children) {
log_assert(child->type == AST::AST_MODULE); if (child->type == AST::AST_MODULE)
for (auto &attr : attributes) for (auto &attr : attributes)
if (child->attributes.count(attr) == 0) if (child->attributes.count(attr) == 0)
child->attributes[attr] = AST::AstNode::mkconst_int(1, false); child->attributes[attr] = AST::AstNode::mkconst_int(1, false);
} }
AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire); AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef, flag_defer, default_nettype_wire);