mirror of https://github.com/YosysHQ/yosys.git
abstract: -state allow partial abstraction, don't use buffer-normalized mode
This commit is contained in:
Emil J. Tywoniak
parent
6027030215
commit
387d0de383
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@ -5,10 +5,82 @@
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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bool abstract_state(Module* mod, Cell* cell, Wire* enable, bool enable_pol) {
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struct EnableLogic {
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Wire* wire;
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bool pol;
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};
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bool abstract_state_port(FfData& ff, SigSpec& port_sig, std::set<int> offsets, EnableLogic enable) {
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// Construct abstract value
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auto anyseq = ff.module->Anyseq(NEW_ID, offsets.size());
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Wire* abstracted = ff.module->addWire(NEW_ID, offsets.size());
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SigSpec mux_input;
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int abstracted_idx = 0;
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for (int d_idx = 0; d_idx < ff.width; d_idx++) {
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if (offsets.count(d_idx)) {
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log_debug("bit %d: abstracted\n", d_idx);
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mux_input.append(port_sig[d_idx]);
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port_sig[d_idx].wire = abstracted;
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port_sig[d_idx].offset = abstracted_idx;
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log_assert(abstracted_idx < abstracted->width);
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abstracted_idx++;
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}
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}
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SigSpec mux_a, mux_b;
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if (enable.pol) {
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mux_a = mux_input;
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mux_b = anyseq;
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} else {
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mux_a = anyseq;
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mux_b = mux_input;
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}
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(void)ff.module->addMux(NEW_ID,
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mux_a,
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mux_b,
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enable.wire,
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abstracted);
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(void)ff.emit();
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return true;
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}
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unsigned int abstract_state(Module* mod, EnableLogic enable) {
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CellTypes ct;
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ct.setup_internals_ff();
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SigMap sigmap(mod);
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pool<SigBit> selected_representatives;
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// Collect reps for all wire bits of selected wires
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for (auto wire : mod->selected_wires())
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for (auto bit : sigmap(wire))
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selected_representatives.insert(bit);
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// Collect reps for all output wire bits of selected cells
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for (auto cell : mod->selected_cells())
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for (auto conn : cell->connections())
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if (cell->output(conn.first))
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for (auto bit : conn.second.bits())
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selected_representatives.insert(sigmap(bit));
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unsigned int changed = 0;
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std::vector<FfData> ffs;
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// Abstract flop inputs if they're driving a selected output rep
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for (auto cell : mod->cells()) {
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if (!ct.cell_types.count(cell->type))
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continue;
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FfData ff(nullptr, cell);
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if (ff.has_sr)
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log_cmd_error("SR not supported\n");
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ffs.push_back(ff);
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}
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for (auto ff : ffs) {
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// A bit inefficient
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std::set<int> offsets_to_abstract;
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for (auto bit : ff.sig_q)
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if (selected_representatives.count(sigmap(bit)))
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offsets_to_abstract.insert(bit.offset);
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if (offsets_to_abstract.empty())
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continue;
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// Normalize to simpler FF
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ff.unmap_ce();
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@ -16,45 +88,11 @@ bool abstract_state(Module* mod, Cell* cell, Wire* enable, bool enable_pol) {
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if (ff.has_arst)
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ff.arst_to_aload();
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// Construct abstract value
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auto anyseq = mod->Anyseq(NEW_ID, ff.width);
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if (ff.has_aload) {
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// ad := enable ? anyseq : ad
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Wire* abstracted_ad = mod->addWire(NEW_ID, ff.sig_ad.size());
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SigSpec mux_a, mux_b;
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if (enable_pol) {
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mux_a = ff.sig_ad;
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mux_b = anyseq;
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} else {
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mux_a = anyseq;
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mux_b = ff.sig_ad;
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if (ff.has_aload)
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changed += abstract_state_port(ff, ff.sig_ad, offsets_to_abstract, enable);
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changed += abstract_state_port(ff, ff.sig_d, offsets_to_abstract, enable);
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}
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(void)mod->addMux(NEW_ID,
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mux_a,
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mux_b,
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enable,
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abstracted_ad);
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ff.sig_ad = abstracted_ad;
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}
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// d := enable ? anyseq : d
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Wire* abstracted_d = mod->addWire(NEW_ID, ff.sig_d.size());
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SigSpec mux_a, mux_b;
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if (enable_pol) {
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mux_a = ff.sig_d;
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mux_b = anyseq;
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} else {
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mux_a = anyseq;
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mux_b = ff.sig_d;
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}
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(void)mod->addMux(NEW_ID,
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mux_a,
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mux_b,
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enable,
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abstracted_d);
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ff.sig_d = abstracted_d;
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(void)ff.emit();
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return true;
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return changed;
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}
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struct AbstractPortCtx {
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@ -75,7 +113,7 @@ void collect_selected_ports(AbstractPortCtx& ctx) {
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}
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}
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unsigned int abstract_value(Module* mod, Wire* enable, bool enable_pol) {
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unsigned int abstract_value(Module* mod, EnableLogic enable) {
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AbstractPortCtx ctx {mod, SigMap(mod), {}};
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collect_selected_ports(ctx);
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unsigned int changed = 0;
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@ -89,7 +127,7 @@ unsigned int abstract_value(Module* mod, Wire* enable, bool enable_pol) {
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// in that we reuse the original signal as the mux output,
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// not input
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SigSpec mux_a, mux_b;
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if (enable_pol) {
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if (enable.pol) {
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mux_a = original;
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mux_b = anyseq;
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} else {
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@ -99,7 +137,7 @@ unsigned int abstract_value(Module* mod, Wire* enable, bool enable_pol) {
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(void)mod->addMux(NEW_ID,
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mux_a,
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mux_b,
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enable,
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enable.wire,
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sig);
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changed++;
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}
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@ -174,25 +212,24 @@ struct AbstractPass : public Pass {
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}
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extra_args(args, argidx, design);
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if (mode != State)
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design->bufNormalize(true);
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unsigned int changed = 0;
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if ((mode == State) || (mode == Value)) {
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if (!enable_name.length())
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log_cmd_error("Unspecified enable wire\n");
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CellTypes ct;
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if (mode == State)
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ct.setup_internals_ff();
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for (auto mod : design->selected_modules()) {
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log_debug("module %s\n", mod->name.c_str());
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Wire *enable_wire = mod->wire("\\" + enable_name);
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if (!enable_wire)
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log_cmd_error("Enable wire %s not found in module %s\n", enable_name.c_str(), mod->name.c_str());
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if (mode == State) {
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for (auto cell : mod->selected_cells())
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if (ct.cell_types.count(cell->type))
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changed += abstract_state(mod, cell, enable_wire, enable_pol);
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// for (auto cell : mod->selected_cells())
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// if (ct.cell_types.count(cell->type))
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changed += abstract_state(mod, {enable_wire, enable_pol});
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} else {
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changed += abstract_value(mod, enable_wire, enable_pol);
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changed += abstract_value(mod, {enable_wire, enable_pol});
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}
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}
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if (mode == State)
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@ -207,6 +244,7 @@ struct AbstractPass : public Pass {
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} else {
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log_cmd_error("No mode selected, see help message\n");
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}
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if (mode != State)
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design->bufNormalize(false);
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}
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} AbstractPass;
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@ -15,6 +15,27 @@ abstract -state -enablen magic
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check -assert
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# show -prefix after_base
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design -reset
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read_verilog <<EOT
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module fff (CLK, DDD, QQQ, Q, magic);
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input CLK;
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input [2:0] DDD;
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output reg [2:0] QQQ;
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output reg Q;
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input magic;
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always @(posedge CLK)
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QQQ <= DDD;
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assign Q = QQQ[0];
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endmodule
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EOT
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proc
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# show -prefix before_wide
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abstract -state -enablen magic w:Q
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# show -prefix after_wide
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check -assert
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design -reset
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read_verilog <<EOT
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module half_clock_en (CLK, E, Q, magic);
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