From 3861cc31f0dc625ee48e7cc1a62e1f2fd7bd324d Mon Sep 17 00:00:00 2001 From: AdamHillier Date: Wed, 19 Apr 2023 11:00:51 +0000 Subject: [PATCH] Add outputs before inputs to the sigmap in the AIGER backend. --- backends/aiger/aiger.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/backends/aiger/aiger.cc b/backends/aiger/aiger.cc index 4ef28be9f..97acf937c 100644 --- a/backends/aiger/aiger.cc +++ b/backends/aiger/aiger.cc @@ -119,16 +119,16 @@ struct AigerWriter if (wire->name.isPublic()) sigmap.add(wire); - // promote input wires - for (auto wire : module->wires()) - if (wire->port_input) - sigmap.add(wire); - // promote output wires for (auto wire : module->wires()) if (wire->port_output) sigmap.add(wire); + // promote input wires + for (auto wire : module->wires()) + if (wire->port_input) + sigmap.add(wire); + for (auto wire : module->wires()) { if (wire->attributes.count(ID::init)) {