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Update CHANGELOG

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Miodrag Milanovic 2022-03-02 14:26:15 +01:00
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CHANGELOG
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@ -5,6 +5,11 @@ List of major changes and improvements between releases
Yosys 0.14 .. Yosys 0.14-dev Yosys 0.14 .. Yosys 0.14-dev
-------------------------- --------------------------
* Various
- clk2fflogic: nice names for autogenerated signals
- simulation include support for all flip-flop types.
- Added AIGER witness file co-simulation.
* Verilog * Verilog
- Fixed evaluation of constant functions with variables or arguments with - Fixed evaluation of constant functions with variables or arguments with
reversed dimensions reversed dimensions
@ -14,6 +19,13 @@ Yosys 0.14 .. Yosys 0.14-dev
* SystemVerilog * SystemVerilog
- Added support for accessing whole sub-structures in expressions - Added support for accessing whole sub-structures in expressions
* New commands and options
- Added glift command, used to create gate-level information flow tracking
(GLIFT) models by the "constructive mapping" approach
* Verific support
- Ability to override default parser mode for verific -f command.
Yosys 0.13 .. Yosys 0.14 Yosys 0.13 .. Yosys 0.14
-------------------------- --------------------------