riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Retry getting rid of write_xaiger's holes_mode

This commit is contained in:
Eddie Hung 2019-12-31 09:59:17 -08:00
parent 436c96e2fb
commit 3798fa3bea
1 changed files with 41 additions and 81 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

122
backends/aiger/xaiger.cc
View File

@ -136,11 +136,10 @@ struct XAigerWriter
return a; return a;
} }
XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module) XAigerWriter(Module *module) : module(module), sigmap(module)
{ {
pool<SigBit> undriven_bits; pool<SigBit> undriven_bits;
pool<SigBit> unused_bits; pool<SigBit> unused_bits;
pool<SigBit> inout_bits;
// promote public wires // promote public wires
for (auto wire : module->wires()) for (auto wire : module->wires())
@ -157,7 +156,12 @@ struct XAigerWriter
if (wire->get_bool_attribute(ID::keep)) if (wire->get_bool_attribute(ID::keep))
sigmap.add(wire); sigmap.add(wire);
for (auto wire : module->wires()) // First, collect all the ports in port_id order
// since module->wires() could be sorted
// alphabetically
for (auto port : module->ports) {
auto wire = module->wire(port);
log_assert(wire);
for (int i = 0; i < GetSize(wire); i++) for (int i = 0; i < GetSize(wire); i++)
{ {
SigBit wirebit(wire, i); SigBit wirebit(wire, i);
@ -166,30 +170,32 @@ struct XAigerWriter
if (bit.wire == nullptr) { if (bit.wire == nullptr) {
if (wire->port_output) { if (wire->port_output) {
aig_map[wirebit] = (bit == State::S1) ? 1 : 0; aig_map[wirebit] = (bit == State::S1) ? 1 : 0;
if (holes_mode) output_bits.insert(wirebit);
output_bits.insert(wirebit);
//external_bits.insert(wirebit);
} }
continue; continue;
} }
undriven_bits.insert(bit);
unused_bits.insert(bit);
if (wire->port_input) if (wire->port_input)
input_bits.insert(bit); input_bits.insert(bit);
if (wire->port_output) { if (wire->port_output) {
if (bit != wirebit) if (bit != wirebit)
alias_map[wirebit] = bit; alias_map[wirebit] = bit;
if (holes_mode) output_bits.insert(wirebit);
output_bits.insert(wirebit);
else
external_bits.insert(wirebit);
} }
}
}
if (wire->port_input && wire->port_output) for (auto wire : module->wires())
inout_bits.insert(wirebit); for (int i = 0; i < GetSize(wire); i++)
{
SigBit wirebit(wire, i);
SigBit bit = sigmap(wirebit);
if (bit.wire) {
undriven_bits.insert(bit);
unused_bits.insert(bit);
}
} }
// TODO: Speed up toposort -- ultimately we care about // TODO: Speed up toposort -- ultimately we care about
@ -207,11 +213,9 @@ struct XAigerWriter
unused_bits.erase(A); unused_bits.erase(A);
undriven_bits.erase(Y); undriven_bits.erase(Y);
not_map[Y] = A; not_map[Y] = A;
if (!holes_mode) { toposort.node(cell->name);
toposort.node(cell->name); bit_users[A].insert(cell->name);
bit_users[A].insert(cell->name); bit_drivers[Y].insert(cell->name);
bit_drivers[Y].insert(cell->name);
}
continue; continue;
} }
@ -224,17 +228,13 @@ struct XAigerWriter
unused_bits.erase(B); unused_bits.erase(B);
undriven_bits.erase(Y); undriven_bits.erase(Y);
and_map[Y] = make_pair(A, B); and_map[Y] = make_pair(A, B);
if (!holes_mode) { toposort.node(cell->name);
toposort.node(cell->name); bit_users[A].insert(cell->name);
bit_users[A].insert(cell->name); bit_users[B].insert(cell->name);
bit_users[B].insert(cell->name); bit_drivers[Y].insert(cell->name);
bit_drivers[Y].insert(cell->name);
}
continue; continue;
} }
log_assert(!holes_mode);
if (cell->type == "$__ABC9_FF_") if (cell->type == "$__ABC9_FF_")
{ {
SigBit D = sigmap(cell->getPort("\\D").as_bit()); SigBit D = sigmap(cell->getPort("\\D").as_bit());
@ -298,7 +298,7 @@ struct XAigerWriter
if (!is_input && !is_output) if (!is_input && !is_output)
log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type)); log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
if (is_input) { if (is_input)
for (auto b : c.second) { for (auto b : c.second) {
Wire *w = b.wire; Wire *w = b.wire;
if (!w) continue; if (!w) continue;
@ -306,13 +306,9 @@ struct XAigerWriter
SigBit I = sigmap(b); SigBit I = sigmap(b);
if (I != b) if (I != b)
alias_map[b] = I; alias_map[b] = I;
if (holes_mode) output_bits.insert(b);
output_bits.insert(b);
else
external_bits.insert(b);
} }
} }
}
} }
//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell)); //log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
@ -495,29 +491,6 @@ struct XAigerWriter
// TODO: Free memory from toposort, bit_drivers, bit_users // TODO: Free memory from toposort, bit_drivers, bit_users
} }
if (!holes_mode)
for (auto cell : module->cells())
if (!module->selected(cell))
for (auto &conn : cell->connections())
if (cell->input(conn.first))
for (auto wirebit : conn.second)
if (sigmap(wirebit).wire)
external_bits.insert(wirebit);
// For all bits consumed outside of the selected cells,
// but driven from a selected cell, then add it as
// a primary output
for (auto wirebit : external_bits) {
SigBit bit = sigmap(wirebit);
if (!bit.wire)
continue;
if (!undriven_bits.count(bit)) {
if (bit != wirebit)
alias_map[wirebit] = bit;
output_bits.insert(wirebit);
}
}
for (auto bit : input_bits) for (auto bit : input_bits)
undriven_bits.erase(sigmap(bit)); undriven_bits.erase(sigmap(bit));
for (auto bit : output_bits) for (auto bit : output_bits)
@ -526,33 +499,18 @@ struct XAigerWriter
undriven_bits.erase(bit); undriven_bits.erase(bit);
// Make all undriven bits a primary input // Make all undriven bits a primary input
if (!holes_mode) for (auto bit : undriven_bits) {
for (auto bit : undriven_bits) { input_bits.insert(bit);
input_bits.insert(bit); undriven_bits.erase(bit);
undriven_bits.erase(bit);
}
if (holes_mode) {
struct sort_by_port_id {
bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
return a.wire->port_id < b.wire->port_id;
}
};
input_bits.sort(sort_by_port_id());
output_bits.sort(sort_by_port_id());
} }
else {
input_bits.sort();
output_bits.sort();
}
not_map.sort();
and_map.sort();
aig_map[State::S0] = 0; aig_map[State::S0] = 0;
aig_map[State::S1] = 1; aig_map[State::S1] = 1;
for (auto bit : input_bits) { // pool<> iterates in LIFO order...
for (int i = input_bits.size()-1; i >= 0; i--) {
const auto &bit = *input_bits.element(i);
log_dump(bit, i);
aig_m++, aig_i++; aig_m++, aig_i++;
log_assert(!aig_map.count(bit)); log_assert(!aig_map.count(bit));
aig_map[bit] = 2*aig_m; aig_map[bit] = 2*aig_m;
@ -578,7 +536,9 @@ struct XAigerWriter
aig_outputs.push_back(bit2aig(bit)); aig_outputs.push_back(bit2aig(bit));
} }
for (auto bit : output_bits) { // pool<> iterates in LIFO order...
for (int i = output_bits.size()-1; i >= 0; i--) {
const auto &bit = *output_bits.element(i);
ordered_outputs[bit] = aig_o++; ordered_outputs[bit] = aig_o++;
aig_outputs.push_back(bit2aig(bit)); aig_outputs.push_back(bit2aig(bit));
} }
@ -877,7 +837,7 @@ struct XAigerWriter
Pass::call(holes_design, "opt -purge"); Pass::call(holes_design, "opt -purge");
std::stringstream a_buffer; std::stringstream a_buffer;
XAigerWriter writer(holes_module, true /* holes_mode */); XAigerWriter writer(holes_module);
writer.write_aiger(a_buffer, false /*ascii_mode*/); writer.write_aiger(a_buffer, false /*ascii_mode*/);
delete holes_design; delete holes_design;