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Added read_verilog -icells option

This commit is contained in:
Clifford Wolf 2014-01-29 00:59:28 +01:00
parent a86f33653d
commit 375c4dddc1
4 changed files with 20 additions and 6 deletions
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8
frontends/ast/ast.cc
View File

@ -46,7 +46,7 @@ namespace AST {
// instanciate global variables (private API) // instanciate global variables (private API)
namespace AST_INTERNAL { namespace AST_INTERNAL {
bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt; bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells;
AstNode *current_ast, *current_ast_mod; AstNode *current_ast, *current_ast_mod;
std::map<std::string, AstNode*> current_scope; std::map<std::string, AstNode*> current_scope;
RTLIL::SigSpec *genRTLIL_subst_from = NULL; RTLIL::SigSpec *genRTLIL_subst_from = NULL;
@ -826,11 +826,12 @@ static AstModule* process_module(AstNode *ast)
current_module->mem2reg = flag_mem2reg; current_module->mem2reg = flag_mem2reg;
current_module->lib = flag_lib; current_module->lib = flag_lib;
current_module->noopt = flag_noopt; current_module->noopt = flag_noopt;
current_module->icells = flag_icells;
return current_module; return current_module;
} }
// create AstModule instances for all modules in the AST tree and add them to 'design' // create AstModule instances for all modules in the AST tree and add them to 'design'
void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool ignore_redef) void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool nolatches, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool ignore_redef)
{ {
current_ast = ast; current_ast = ast;
flag_dump_ast1 = dump_ast1; flag_dump_ast1 = dump_ast1;
@ -841,6 +842,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump
flag_mem2reg = mem2reg; flag_mem2reg = mem2reg;
flag_lib = lib; flag_lib = lib;
flag_noopt = noopt; flag_noopt = noopt;
flag_icells = icells;
assert(current_ast->type == AST_DESIGN); assert(current_ast->type == AST_DESIGN);
for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) { for (auto it = current_ast->children.begin(); it != current_ast->children.end(); it++) {
@ -877,6 +879,7 @@ RTLIL::IdString AstModule::derive(RTLIL::Design *design, std::map<RTLIL::IdStrin
flag_mem2reg = mem2reg; flag_mem2reg = mem2reg;
flag_lib = lib; flag_lib = lib;
flag_noopt = noopt; flag_noopt = noopt;
flag_icells = icells;
use_internal_line_num(); use_internal_line_num();
std::string para_info; std::string para_info;
@ -959,6 +962,7 @@ RTLIL::Module *AstModule::clone() const
new_mod->mem2reg = mem2reg; new_mod->mem2reg = mem2reg;
new_mod->lib = lib; new_mod->lib = lib;
new_mod->noopt = noopt; new_mod->noopt = noopt;
new_mod->icells = icells;
return new_mod; return new_mod;
} }

6
frontends/ast/ast.h
View File

@ -231,13 +231,13 @@ namespace AST
}; };
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false, bool ignore_redef = false); void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1 = false, bool dump_ast2 = false, bool dump_vlog = false, bool nolatches = false, bool nomem2reg = false, bool mem2reg = false, bool lib = false, bool noopt = false, bool icells = false, bool ignore_redef = false);
// parametric modules are supported directly by the AST library // parametric modules are supported directly by the AST library
// therfore we need our own derivate of RTLIL::Module with overloaded virtual functions // therfore we need our own derivate of RTLIL::Module with overloaded virtual functions
struct AstModule : RTLIL::Module { struct AstModule : RTLIL::Module {
AstNode *ast; AstNode *ast;
bool nolatches, nomem2reg, mem2reg, lib, noopt; bool nolatches, nomem2reg, mem2reg, lib, noopt, icells;
virtual ~AstModule(); virtual ~AstModule();
virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters); virtual RTLIL::IdString derive(RTLIL::Design *design, std::map<RTLIL::IdString, RTLIL::Const> parameters);
virtual RTLIL::Module *clone() const; virtual RTLIL::Module *clone() const;
@ -258,7 +258,7 @@ namespace AST
namespace AST_INTERNAL namespace AST_INTERNAL
{ {
// internal state variables // internal state variables
extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt; extern bool flag_dump_ast1, flag_dump_ast2, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells;
extern AST::AstNode *current_ast, *current_ast_mod; extern AST::AstNode *current_ast, *current_ast_mod;
extern std::map<std::string, AST::AstNode*> current_scope; extern std::map<std::string, AST::AstNode*> current_scope;
extern RTLIL::SigSpec *genRTLIL_subst_from, *genRTLIL_subst_to, ignoreThisSignalsInInitial; extern RTLIL::SigSpec *genRTLIL_subst_from, *genRTLIL_subst_to, ignoreThisSignalsInInitial;

2
frontends/ast/genrtlil.cc
View File

@ -1334,6 +1334,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
AstNode *child = *it; AstNode *child = *it;
if (child->type == AST_CELLTYPE) { if (child->type == AST_CELLTYPE) {
cell->type = child->str; cell->type = child->str;
if (flag_icells && cell->type.substr(0, 2) == "\\$")
cell->type = cell->type.substr(1);
continue; continue;
} }
if (child->type == AST_PARASET) { if (child->type == AST_PARASET) {

10
frontends/verilog/verilog_frontend.cc
View File

@ -99,6 +99,9 @@ struct VerilogFrontend : public Frontend {
log(" don't perform basic optimizations (such as const folding) in the\n"); log(" don't perform basic optimizations (such as const folding) in the\n");
log(" high-level front-end.\n"); log(" high-level front-end.\n");
log("\n"); log("\n");
log(" -icells\n");
log(" interpret cell types starting with '$' as internal cell types\n");
log("\n");
log(" -ignore_redef\n"); log(" -ignore_redef\n");
log(" ignore re-definitions of modules. (the default behavior is to\n"); log(" ignore re-definitions of modules. (the default behavior is to\n");
log(" create an error message.)\n"); log(" create an error message.)\n");
@ -127,6 +130,7 @@ struct VerilogFrontend : public Frontend {
bool flag_nopp = false; bool flag_nopp = false;
bool flag_lib = false; bool flag_lib = false;
bool flag_noopt = false; bool flag_noopt = false;
bool flag_icells = false;
bool flag_ignore_redef = false; bool flag_ignore_redef = false;
std::map<std::string, std::string> defines_map; std::map<std::string, std::string> defines_map;
std::list<std::string> include_dirs; std::list<std::string> include_dirs;
@ -183,6 +187,10 @@ struct VerilogFrontend : public Frontend {
flag_noopt = true; flag_noopt = true;
continue; continue;
} }
if (arg == "-icells") {
flag_icells = true;
continue;
}
if (arg == "-ignore_redef") { if (arg == "-ignore_redef") {
flag_ignore_redef = true; flag_ignore_redef = true;
continue; continue;
@ -228,7 +236,7 @@ struct VerilogFrontend : public Frontend {
frontend_verilog_yyparse(); frontend_verilog_yyparse();
frontend_verilog_yylex_destroy(); frontend_verilog_yylex_destroy();
AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_ignore_redef); AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_nolatches, flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_ignore_redef);
if (!flag_nopp) if (!flag_nopp)
fclose(fp); fclose(fp);