mirror of https://github.com/YosysHQ/yosys.git
Automatically pack SigSpec on copy/assign
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e75e495c2b
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3719281ed4
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@ -1518,6 +1518,48 @@ RTLIL::SigSpec::SigSpec()
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hash_ = 0;
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hash_ = 0;
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}
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}
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RTLIL::SigSpec::SigSpec(const RTLIL::SigSpec &other)
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{
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*this = other;
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}
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const RTLIL::SigSpec &RTLIL::SigSpec::operator=(const RTLIL::SigSpec &other)
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{
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cover("kernel.rtlil.sigspec.assign");
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width_ = other.width_;
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hash_ = other.hash_;
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chunks_ = other.chunks_;
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bits_.clear();
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if (!other.bits_.empty())
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{
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RTLIL::SigChunk *last = NULL;
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int last_end_offset = 0;
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for (auto &bit : other.bits_) {
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if (last && bit.wire == last->wire) {
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if (bit.wire == NULL) {
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last->data.bits.push_back(bit.data);
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last->width++;
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continue;
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} else if (last_end_offset == bit.offset) {
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last_end_offset++;
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last->width++;
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continue;
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}
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}
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chunks_.push_back(bit);
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last = &chunks_.back();
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last_end_offset = bit.offset + 1;
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}
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check();
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}
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return *this;
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}
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RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
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RTLIL::SigSpec::SigSpec(const RTLIL::Const &value)
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{
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{
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chunks_.push_back(RTLIL::SigChunk(value));
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chunks_.push_back(RTLIL::SigChunk(value));
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@ -1626,24 +1668,25 @@ void RTLIL::SigSpec::pack() const
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std::vector<RTLIL::SigBit> old_bits;
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std::vector<RTLIL::SigBit> old_bits;
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old_bits.swap(that->bits_);
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old_bits.swap(that->bits_);
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RTLIL::SigChunk *last_const = NULL;
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RTLIL::SigChunk *last = NULL;
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RTLIL::SigChunk *last_wire = NULL;
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int last_end_offset = 0;
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int last_wire_end = 0;
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for (auto &bit : old_bits)
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for (auto &bit : old_bits) {
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if (bit.wire == NULL && last_const) {
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if (last && bit.wire == last->wire) {
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last_const->data.bits.push_back(bit.data);
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if (bit.wire == NULL) {
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last_const->width++;
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last->data.bits.push_back(bit.data);
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} else
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last->width++;
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if (bit.wire && last_wire && last_wire->wire == bit.wire && last_wire_end == bit.offset) {
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continue;
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last_wire->width++;
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} else if (last_end_offset == bit.offset) {
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last_wire_end++;
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last_end_offset++;
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} else {
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last->width++;
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that->chunks_.push_back(bit);
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continue;
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last_const = bit.wire ? NULL : &that->chunks_.back();
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}
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last_wire = bit.wire ? &that->chunks_.back() : NULL;
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last_wire_end = bit.offset + 1;
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}
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}
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that->chunks_.push_back(bit);
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last = &that->chunks_.back();
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last_end_offset = bit.offset + 1;
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}
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check();
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check();
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}
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}
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@ -567,6 +567,9 @@ private:
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public:
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public:
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SigSpec();
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SigSpec();
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SigSpec(const RTLIL::SigSpec &other);
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const RTLIL::SigSpec &operator=(const RTLIL::SigSpec &other);
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SigSpec(const RTLIL::Const &value);
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SigSpec(const RTLIL::Const &value);
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SigSpec(const RTLIL::SigChunk &chunk);
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SigSpec(const RTLIL::SigChunk &chunk);
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SigSpec(RTLIL::Wire *wire);
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SigSpec(RTLIL::Wire *wire);
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