riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Fix spacing

This commit is contained in:
Eddie Hung 2019-04-08 16:37:22 -07:00
parent bca3cf6843
commit 36efec01b8
1 changed files with 29 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

58
frontends/aiger/aigerparse.cc
View File

@ -805,13 +805,13 @@ struct AigerFrontend : public Frontend {
log(" AIGER latches to be transformed into posedge DFFs clocked by wire of"); log(" AIGER latches to be transformed into posedge DFFs clocked by wire of");
log(" this name (default: clk)\n"); log(" this name (default: clk)\n");
log("\n"); log("\n");
log(" -map <filename>\n"); log(" -map <filename>\n");
log(" read file with port and latch symbols\n"); log(" read file with port and latch symbols\n");
log("\n");
log(" -wideports\n");
log(" Merge ports that match the pattern 'name[int]' into a single\n");
log(" multi-bit port 'name'.\n");
log("\n"); log("\n");
log(" -wideports\n");
log(" Merge ports that match the pattern 'name[int]' into a single\n");
log(" multi-bit port 'name'.\n");
log("\n");
} }
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
{ {
@ -822,28 +822,28 @@ struct AigerFrontend : public Frontend {
std::string map_filename; std::string map_filename;
bool wideports = false; bool wideports = false;
size_t argidx; size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) { for (argidx = 1; argidx < args.size(); argidx++) {
std::string arg = args[argidx]; std::string arg = args[argidx];
if (arg == "-module_name" && argidx+1 < args.size()) { if (arg == "-module_name" && argidx+1 < args.size()) {
module_name = RTLIL::escape_id(args[++argidx]); module_name = RTLIL::escape_id(args[++argidx]);
continue; continue;
} }
if (arg == "-clk_name" && argidx+1 < args.size()) { if (arg == "-clk_name" && argidx+1 < args.size()) {
clk_name = RTLIL::escape_id(args[++argidx]); clk_name = RTLIL::escape_id(args[++argidx]);
continue; continue;
} }
if (map_filename.empty() && arg == "-map" && argidx+1 < args.size()) { if (map_filename.empty() && arg == "-map" && argidx+1 < args.size()) {
map_filename = args[++argidx]; map_filename = args[++argidx];
continue; continue;
} }
if (arg == "-wideports") { if (arg == "-wideports") {
wideports = true; wideports = true;
continue; continue;
} }
break; break;
} }
extra_args(f, filename, args, argidx); extra_args(f, filename, args, argidx);
if (module_name.empty()) { if (module_name.empty()) {
#ifdef _WIN32 #ifdef _WIN32
@ -858,7 +858,7 @@ struct AigerFrontend : public Frontend {
} }
AigerReader reader(design, *f, module_name, clk_name, map_filename, wideports); AigerReader reader(design, *f, module_name, clk_name, map_filename, wideports);
reader.parse_aiger(); reader.parse_aiger();
} }
} AigerFrontend; } AigerFrontend;