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Add warning for SV "restrict" without "property" 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-11-04 15:57:17 +01:00
parent d0acea4f2e
commit 36ea98385f
1 changed files with 11 additions and 2 deletions
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13
frontends/verilog/verilog_parser.y
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@ -125,7 +125,7 @@ static void free_attr(std::map<std::string, AstNode*> *al)
%type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int %type <ast> range range_or_multirange non_opt_range non_opt_multirange range_or_signed_int
%type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list %type <ast> wire_type expr basic_expr concat_list rvalue lvalue lvalue_concat_list
%type <string> opt_label tok_prim_wrapper hierarchical_id %type <string> opt_label tok_prim_wrapper hierarchical_id
%type <boolean> opt_signed unique_case_attr %type <boolean> opt_signed opt_property unique_case_attr
%type <al> attr case_attr %type <al> attr case_attr
// operator precedence from low to high // operator precedence from low to high
@ -1320,7 +1320,12 @@ opt_label:
}; };
opt_property: opt_property:
TOK_PROPERTY | /* empty */; TOK_PROPERTY {
$$ = true;
} |
/* empty */ {
$$ = false;
};
opt_stmt_label: opt_stmt_label:
TOK_ID ':' | /* empty */; TOK_ID ':' | /* empty */;
@ -1399,12 +1404,16 @@ assert:
delete $5; delete $5;
else else
ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5)); ast_stack.back()->children.push_back(new AstNode(AST_ASSUME, $5));
if (!$3)
log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
} | } |
opt_stmt_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' { opt_stmt_label TOK_RESTRICT opt_property '(' TOK_EVENTUALLY expr ')' ';' {
if (norestrict_mode) if (norestrict_mode)
delete $6; delete $6;
else else
ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6)); ast_stack.back()->children.push_back(new AstNode(AST_FAIR, $6));
if (!$3)
log_file_warning(current_filename, get_line_num(), "SystemVerilog does not allow \"restrict\" without \"property\".\n");
}; };
assert_property: assert_property: