mirror of https://github.com/YosysHQ/yosys.git
Fix more potential for undefined behaviour due to container invalidation
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03705f69f4
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@ -436,14 +436,18 @@ struct XAigerWriter
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new_wire = module->addWire(wire_name, GetSize(wire));
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new_wire = module->addWire(wire_name, GetSize(wire));
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SigBit new_bit(new_wire, bit.offset);
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SigBit new_bit(new_wire, bit.offset);
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module->connect(new_bit, bit);
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module->connect(new_bit, bit);
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if (not_map.count(bit))
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if (not_map.count(bit)) {
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not_map[new_bit] = not_map.at(bit);
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auto a = not_map.at(bit);
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else if (and_map.count(bit)) {
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not_map[new_bit] = a;
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//and_map[new_bit] = and_map.at(bit); // Breaks gcc-4.8
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}
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and_map.insert(std::make_pair(new_bit, and_map.at(bit)));
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else if (and_map.count(bit)) {
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auto a = and_map.at(bit);
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and_map[new_bit] = a;
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}
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else if (alias_map.count(bit)) {
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auto a = alias_map.at(bit);
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alias_map[new_bit] = a;
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}
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}
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else if (alias_map.count(bit))
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alias_map[new_bit] = alias_map.at(bit);
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else
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else
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alias_map[new_bit] = bit;
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alias_map[new_bit] = bit;
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output_bits.erase(bit);
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output_bits.erase(bit);
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